Patents by Inventor Chien-Yu Chen

Chien-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240297067
    Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.
    Type: Application
    Filed: May 15, 2024
    Publication date: September 5, 2024
    Inventors: Kun-Huang Yu, Chien-Yu Chen, Ting-Wei Liao, Chih-Wen Hsiung, Chun-Lung Chang, Kuo-Chin Chiu, Wu-Te Weng, Chien-Wei Chiu, Yong-Zhong Hu, Ta-Yung Yang
  • Patent number: 12062585
    Abstract: A wafer includes a plurality of testing dies, a plurality of non-testing dies, and a dicing region. Each testing die includes: a first active area including one or more first active devices, and one or more first device pads electrically coupled to the one or more first active devices. Each non-testing die includes: a second active area including one or more second active devices, and one or more second device pads electrically coupled to the one or more second active devices. The dicing region includes one or more testing pads electrically coupled to the one or more first device pads. The one or more testing pads are arranged to receive one or more external probes for determining one or more characteristics of the one or more first active devices of the plurality of testing dies. The plurality of non-testing dies are electrically isolated from the dicing region.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: August 13, 2024
    Assignee: ARTILUX, INC.
    Inventors: Chien-Yu Chen, Yi-Chuan Teng, Yu-Hsuan Liu, Yun-Chung Na
  • Patent number: 12062570
    Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: August 13, 2024
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Kun-Huang Yu, Chien-Yu Chen, Ting-Wei Liao, Chih-Wen Hsiung, Chun-Lung Chang, Kuo-Chin Chiu, Wu-Te Weng, Chien-Wei Chiu, Yong-Zhong Hu, Ta-Yung Yang
  • Publication number: 20240248501
    Abstract: A reference voltage generator circuit includes: a first transistor and a second transistor, wherein the first transistor and the second transistor are coupled with each other and are located on a substrate, wherein the first transistor has a first conduction threshold voltage and a first rated voltage, wherein the second transistor has a second conduction threshold voltage and a second rated voltage, wherein the first rated voltage is higher than the second rated voltage; wherein the reference voltage generator circuit is configured to generate a bandgap reference voltage with temperature compensation according to a difference between the first conduction threshold voltage and the second conduction threshold voltage.
    Type: Application
    Filed: October 17, 2023
    Publication date: July 25, 2024
    Inventors: Chien-Yu Chen, Li Lin, Cheng-Kuang Lin, Yue-Hung Tang, Ting-Wei Liao, Shao-Hung Lu
  • Publication number: 20240230401
    Abstract: The present disclosure provides a test system and method. The test system is configured to analyze a system platform and includes a data collector and a test monitor. The data collector is configured to receive a signal transmitted between a controller and a memory of the system platform and is configured to process the signal to generate a processed signal. The test monitor is configured to encode the processed signal into a log information, so as to determine an operation status of the system platform according to the log information.
    Type: Application
    Filed: October 19, 2022
    Publication date: July 11, 2024
    Inventors: Chien Yu CHEN, Meng-Kai HSIEH
  • Patent number: 12013463
    Abstract: A photo-detecting apparatus is provided. The photo-detecting apparatus includes: a substrate made by a first material or a first material-composite; an absorption layer made by a second material or a second material-composite, the absorption layer being supported by the substrate and the absorption layer including: a first surface; a second surface arranged between the first surface and the substrate; and a channel region having a dopant profile with a peak dopant concentration equal to or more than 1×1015 cm?3, wherein a distance between the first surface and a location of the channel region having the peak dopant concentration is less than a distance between the second surface and the location of the channel region having the peak dopant concentration, and wherein the distance between the first surface and the location of the channel region having the peak dopant concentration is not less than 30 nm.
    Type: Grant
    Filed: March 14, 2023
    Date of Patent: June 18, 2024
    Assignee: Artilux, Inc.
    Inventors: Szu-Lin Cheng, Chien-Yu Chen, Shu-Lu Chen, Yun-Chung Na, Ming-Jay Yang, Han-Din Liu, Che-Fu Liang, Jung-Chin Chiang, Yen-Cheng Lu, Yen-Ju Lin
  • Patent number: 12000756
    Abstract: A leakage detection system is provided and includes a substrate provided between a first element and a second element, and at least one sensing unit provided on the substrate to generate an electrical signal when coming into contact with a leakage liquid. As such, warnings can be provided when coming into contact with the leakage liquid to avoid significant loss of assets.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: June 4, 2024
    Assignee: AURAS TECHNOLOGY CO., LTD.
    Inventors: Chien-Yu Chen, Tian-Li Ye, Jen-Hao Lin, Wei-Shen Lee
  • Patent number: 11991860
    Abstract: A fluid cooling device includes a bottom plate, an adhesive layer and a spray cooling cover. The bottom plate includes a substrate and a chip, and the spray cooling cover is fixed on the bottom plate by an adhesive layer. In addition, the spray cooling cover includes a fluid inlet and a plurality of fluid outlets to utilize a working fluid to cool the chip directly.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: May 21, 2024
    Assignee: AURAS TECHNOLOGY CO., LTD.
    Inventors: Chien-Yu Chen, Wei-Hao Chen
  • Publication number: 20240161857
    Abstract: The present disclosure provides a memory testing system, including at least one memory device, a power supply, and a processor. The power supply is configured to provide a first reference voltage to the at least one memory device according to a control signal. The processor is configured to provide the control signal to control the power supply to vary the first reference voltage among multiple voltage levels and test the at least one memory device under the voltage levels to generate multiple first testing results corresponding to the voltage levels.
    Type: Application
    Filed: November 16, 2022
    Publication date: May 16, 2024
    Inventor: Chien Yu CHEN
  • Publication number: 20240133737
    Abstract: The present disclosure provides a test system and method. The test system is configured to analyze a system platform and includes a data collector and a test monitor. The data collector is configured to receive a signal transmitted between a controller and a memory of the system platform and is configured to process the signal to generate a processed signal. The test monitor is configured to encode the processed signal into a log information, so as to determine an operation status of the system platform according to the log information.
    Type: Application
    Filed: October 18, 2022
    Publication date: April 25, 2024
    Inventors: Chien Yu CHEN, Meng-Kai HSIEH
  • Publication number: 20240118964
    Abstract: A fault analysis device and a fault analysis method of the fault analysis device are provided. A sensing circuit senses a first distorted signal on a first signal transmission path of an abnormal signal device when the abnormal signal device performs a preset operation. A signal generating circuit provides a fault test signal to a second signal transmission path of a standard device corresponding to the first signal transmission path when the standard device performs the preset operation, so as to generate a second distorted signal on the second signal transmission path, where the first distorted signal and the second distorted signal have the same signal distortion characteristics.
    Type: Application
    Filed: October 5, 2022
    Publication date: April 11, 2024
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Chien Yu Chen, Meng-Kai Hsieh
  • Patent number: 11956919
    Abstract: A cold plate is provided and includes: a housing disposed with a chamber; a base combined with the housing to form a working space separated from the chamber but connected with the chamber through an interconnecting structure to allow a working medium to flow within the chamber and the working space; a heat transfer structure disposed on the inner side of the base; and a pump disposed within the working space to drive the working medium in the working space. As such, the cold plate can provide better heat dissipation performance.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: April 9, 2024
    Assignee: AURAS TECHNOLOGY CO., LTD.
    Inventors: Chien-An Chen, Chien-Yu Chen, Tian-Li Ye, Jen-Hao Lin, Wei-Shen Lee
  • Patent number: 11955404
    Abstract: An electronic package includes an electronic component and a heat dissipation structure, wherein the heat dissipation structure has a plurality of bonding pillars, and a metal layer is formed on the bonding pillars, so as to stably dispose the heat dissipation structure on the electronic component via the bonding pillars and the metal layer.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: April 9, 2024
    Assignee: AURAS TECHNOLOGY CO., LTD.
    Inventors: Jian-Dih Jeng, Chien-Yu Chen, Wei-Hao Chen
  • Patent number: 11955890
    Abstract: A switching converter circuit for switching one end of an inductor therein between plural voltages according to a pulse width modulation (PWM) signal to convert an input voltage to an output voltage. The switching converter circuit has a driver circuit including a high side driver, a low side driver, a high side sensor circuit, and a low side sensor circuit. The high side sensor circuit is configured to sense a gate-source voltage of a high side metal oxide semiconductor field effect transistor (MOSFET), to generate a low side enable signal for enabling the low side driver to switch a low side MOSFET according to the PWM signal. The low side sensor circuit is configured to sense a gate-source voltage of a low side MOSFET, to generate a high side enable signal for enabling the high side driver to switch a high side MOSFET according to the PWM signal.
    Type: Grant
    Filed: January 2, 2022
    Date of Patent: April 9, 2024
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Ting-Wei Liao, Chien-Yu Chen, Kun-Huang Yu, Chien-Wei Chiu, Ta-Yung Yang
  • Patent number: 11942857
    Abstract: A power supply is provided. The power supply includes a power supply circuit and a control circuit. The power supply circuit includes a voltage converter and multiple point-of-load circuits. The voltage converter generates a third voltage according to a first voltage. The load point-of-load circuits generate at least one second voltage and at least one state signal according to the third voltage. The at least one second voltage is suitable for supplying power to a load. The control circuit is coupled to the power supply circuit. The control circuit determines whether a single event latch-up occurs in the power supply circuit according to the at least one state signal. When the single event latch-up occurs in the power supply circuit, the control circuit switches off the power supply circuit to stop generating the at least one second voltage and the at least one state signal.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: March 26, 2024
    Assignee: Industrial Technology Research Institute
    Inventors: Cheng-Wei Yang, Chueh-Hao Yu, Chien-Yu Chen
  • Patent number: 11935009
    Abstract: The present invention extends to methods, systems, and computer program products for integrating healthcare screening with other identity-based functions. In general, components facilitating healthcare screening interoperate with and/or are integrated into other systems, including facility access, identity, time keeping, payroll, etc. Aspects of the invention include using facial recognition to improve healthcare screening and satisfy governmental regulations. A thermal scanner can include a camera and an InfraRed (IR) camera. The thermal scanner can collect a facial image and derive a temperature for a person (e.g., from an IR image). The thermal scanner can also collect or access previously collected healthcare screening questionnaire answers. The collected temperate and healthcare screening questionnaire answers can be used to control access to the facility.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: March 19, 2024
    Assignee: TURING VIDEO
    Inventors: Weiwei Chen, Chien-Yu Chen, Zhengyang Ma, Chethan Kothwal
  • Patent number: 11930618
    Abstract: A liquid cooling head includes a bottom plate, a heat dissipation plate, a partition plate and an upper cover plate. The bottom plate includes an opening, and the heat dissipation plate, the partition plate and the upper cover plate are fixed to the bottom plate. The partition plate divides the opening into a plurality of cooling chambers, and each cooling chamber is equipped with a cooling liquid inlet, a cooling liquid outlet, a pump and an electric control device. The cooling liquid inlet and the cooling liquid outlet are formed in the upper cover plate, the pump is fluid-connected to the cooling liquid outlet, and the electric control device drives the pump to rotate, so that the cooling liquid flows through the cooling chamber to cool one heat source below the heat dissipation plate. In addition, a liquid cooling device with the liquid cooling head is also disclosed therein.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: March 12, 2024
    Assignee: AURAS TECHNOLOGY CO., LTD.
    Inventors: Chien-Yu Chen, Tian-Li Ye, Jen-Hao Lin, Chien-An Chen
  • Patent number: 11915666
    Abstract: A display device, a display driving integrated circuit (DDIC), and an operation method are provided. The display device includes a display panel, a first DDIC, and a second DDIC. The first DDIC generates a display synchronization signal, and drives a first display area of a display panel according to the display synchronization signal. The second DDIC is coupled to the first DDIC to receive the display synchronization signal. The second DDIC performs a frequency tracking operation on an internal clock signal of the second DDIC by selectively using the display synchronization signal. The second DDIC drives a second display area of the display panel according to the internal clock signal and the display synchronization signal.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: February 27, 2024
    Assignee: Novatek Microelectronics Corp.
    Inventors: Jung-Hsuan Sung, Kai-Wen Shao, Chien-Yu Chen
  • Patent number: 11906571
    Abstract: An optical detection system and a laser providing module without using an optical fiber thereof are provided. The optical detection system includes a carrier module, a laser light providing module, and an electrical detection module. The carrier module is configured to carry a plurality of photodiodes. The laser light providing module is disposed above the carrier module. The electrical detection module is adjacent to the carrier module. The laser light providing module is configured to convert a laser light source into a plurality of laser light beams, thereby simultaneously and respectively exciting two corresponding ones of the photodiodes. The electrical detection module is configured to simultaneously and electrically contact the corresponding photodiodes so as to obtain an electrical signal generated by each of the photodiodes.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: February 20, 2024
    Assignee: MPI CORPORATION
    Inventors: Chien-Yu Chen, Po-Han Peng
  • Patent number: 11876453
    Abstract: A switching converter circuit, which switches one terminal of an inductor to different voltages, includes a high side MOSFET, a low side MOSFET, and a driver circuit which includes a high side driver, a low side driver, and a dead time control circuit. According to an output current, The dead time control circuit adaptively delays a low side driving signal to generate a high side enable signal for enabling the high side driver to generate a high side driving signal according to a pulse width modulation (PWM) signal; and/or adaptively delays the high side driving signal to generate a low side enable signal for enabling the low side driver to generate the low side driving signal according to the PWM signal, so as to adaptively control a dead time in which the high side MOSFET and the low side MOSFET are both not conductive.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: January 16, 2024
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Ting-Wei Liao, Chien-Yu Chen, Kun-Huang Yu, Chien-Wei Chiu, Ta-Yung Yang