Patents by Inventor Chien-Yu Huang
Chien-Yu Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200388623Abstract: Systems and methods are provided for fabricating a static random access memory (SRAM) cell in a multi-layer semiconductor device structure. An example SRAM device includes a first array of SRAM cells, a second array of SRAM cells, a processing component, and one or more inter-layer connection structures. The first array of SRAM cells are formed in a first device layer of a multi-layer semiconductor device structure. The second array of SRAM cells are formed in a second device layer of the multi-layer semiconductor device structure, the second device layer being formed on the first device layer. The processing component is configured to process one or more input signals and generate one or more access signals. One or more inter-layer connection structures are configured to transmit the one or more access signals to activate the first device layer or the second device layer for allowing access to a target SRAM cell.Type: ApplicationFiled: August 24, 2020Publication date: December 10, 2020Inventors: Chien-Yu Huang, Chien-Yuan Chen, Hau-Tai Shieh
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Patent number: 10756094Abstract: Systems and methods are provided for fabricating a static random access memory (SRAM) cell in a multi-layer semiconductor device structure. An example SRAM device includes a first array of SRAM cells, a second array of SRAM cells, a processing component, and one or more inter-layer connection structures. The first array of SRAM cells are formed in a first device layer of a multi-layer semiconductor device structure. The second array of SRAM cells are formed in a second device layer of the multi-layer semiconductor device structure, the second device layer being formed on the first device layer. The processing component is configured to process one or more input signals and generate one or more access signals. One or more inter-layer connection structures are configured to transmit the one or more access signals to activate the first device layer or the second device layer for allowing access to a target SRAM cell.Type: GrantFiled: April 6, 2018Date of Patent: August 25, 2020Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chien-Yu Huang, Chien-Yuan Chen, Hau-Tai Shieh
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Publication number: 20200251122Abstract: An information handling system audio system includes a library of noise reduction filters associated with cooling fan speeds to isolate out cooling fan noise. Changed cooling fan settings communicated to the audio system trigger application of a library noise reduction filter for the selected cooling fan setting to isolate out cooling fan noise while an adaptive filter defines a noise reduction filter from recorded sounds. The library noise reduction filter reduces cooling fan noises during the time used to determine the adaptive noise reduction filter. In one embodiment, changes in cooling fan settings prioritize definition of noise reduction filters by the adaptive filter.Type: ApplicationFiled: February 4, 2019Publication date: August 6, 2020Applicant: Dell Products L.P.Inventors: Chien-Yu Huang, Shih Chia-Hung, Chu Shu Hsuan
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Patent number: 10671732Abstract: An electronic apparatus and a secure boot method thereof are provided. The electronic apparatus includes at least two connecting devices and a storage device. In the method, a current configuration of the connecting devices is detected, in which the current configuration includes one or a combination of a number, types, specifications and identifications of external devices connected with the connecting devices. Then, multiple preset configurations recorded in the storage device are retrieved and compared with the detected current configuration. If the current configuration matches one of the preset configurations, an apparatus function corresponding to the matched preset configuration is executed.Type: GrantFiled: April 13, 2017Date of Patent: June 2, 2020Assignee: Wistron CorporationInventor: Chien-Yu Huang
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Publication number: 20200020413Abstract: Different embodiments of local redundancy decoder circuits that can be used in a memory device are disclosed. The different types of local redundancy decoder circuits are operably connected to the columns of memory cells in a memory array.Type: ApplicationFiled: July 11, 2019Publication date: January 16, 2020Inventors: Chien-Yu Huang, Chia-En Huang, Cheng Hung Lee, Hau-Tai Shieh
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Patent number: 10354719Abstract: Systems are provided for a three dimension static random access memory (SRAM) structure. The SRAM structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs extending vertically from a memory cell in a first memory array layer to a memory cell in a second memory array layer. The layer decoder circuitry on each memory array layer is configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to memory cells on its memory array layer. The word line driver circuit disposed on each memory array layer is configured to operate cooperatively with a partial SRAM address decoder to select and drive one of the plurality of word lines disposed on its memory array layer, wherein a selected word line is connected to a predetermined number of memory cells in a specific memory array layer.Type: GrantFiled: December 20, 2018Date of Patent: July 16, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chien-Yuan Chen, Chien-Yu Huang, Hau-Tai Shieh
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Publication number: 20190122725Abstract: Systems are provided for a three dimension static random access memory (SRAM) structure. The SRAM structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs extending vertically from a memory cell in a first memory array layer to a memory cell in a second memory array layer. The layer decoder circuitry on each memory array layer is configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to memory cells on its memory array layer. The word line driver circuit disposed on each memory array layer is configured to operate cooperatively with a partial SRAM address decoder to select and drive one of the plurality of word lines disposed on its memory array layer, wherein a selected word line is connected to a predetermined number of memory cells in a specific memory array layer.Type: ApplicationFiled: December 20, 2018Publication date: April 25, 2019Inventors: Chien-Yuan Chen, Chien-Yu Huang, Hau-Tai Shieh
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Publication number: 20190071473Abstract: The present invention provides a modified oleosin protein, a polynucleotide sequence encoding the modified protein, and a method for regulating subcellular lipid distribution by recombinantly expressing the modified oleosin protein. This invention also provides a method for generating cells and organisms comprising the modified oleosin protein and exhibiting an altered subcellular lipid distribution pattern, as well as cells and organisms generated by such a method.Type: ApplicationFiled: May 15, 2018Publication date: March 7, 2019Inventors: Chien Yu Huang, Anthony H.C. Huang
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Patent number: 10163489Abstract: Systems are provided for a three dimension static random access memory (SRAM) structure. The SRAM structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs extending vertically from a memory cell in a first memory array layer to a memory cell in a second memory array layer. The layer decoder circuitry on each memory array layer is configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to memory cells on its memory array layer. The word line driver circuit disposed on each memory array layer is configured to operate cooperatively with a partial SRAM address decoder to select and drive one of the plurality of word lines disposed on its memory array layer, wherein a selected word line is connected to a predetermined number of memory cells in a specific memory array layer.Type: GrantFiled: January 9, 2018Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chien-Yuan Chen, Chien-Yu Huang, Hau-Tai Shieh
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Publication number: 20180226412Abstract: Systems and methods are provided for fabricating a static random access memory (SRAM) cell in a multi-layer semiconductor device structure. An example SRAM device includes a first array of SRAM cells, a second array of SRAM cells, a processing component, and one or more inter-layer connection structures. The first array of SRAM cells are formed in a first device layer of a multi-layer semiconductor device structure. The second array of SRAM cells are formed in a second device layer of the multi-layer semiconductor device structure, the second device layer being formed on the first device layer. The processing component is configured to process one or more input signals and generate one or more access signals. One or more inter-layer connection structures are configured to transmit the one or more access signals to activate the first device layer or the second device layer for allowing access to a target SRAM cell.Type: ApplicationFiled: April 6, 2018Publication date: August 9, 2018Inventors: Chien-Yu Huang, Chien-Yuan Chen, Hau-Tai Shieh
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Publication number: 20180165456Abstract: An electronic apparatus and a secure boot method thereof are provided. The electronic apparatus includes at least two connecting devices and a storage device. In the method, a current configuration of the connecting devices is detected, in which the current configuration includes one or a combination of a number, types, specifications and identifications of external devices connected with the connecting devices. Then, multiple preset configurations recorded in the storage device are retrieved and compared with the detected current configuration. If the current configuration matches one of the preset configurations, an apparatus function corresponding to the matched preset configuration is executed.Type: ApplicationFiled: April 13, 2017Publication date: June 14, 2018Applicant: Wistron CorporationInventor: Chien-Yu Huang
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Publication number: 20180130519Abstract: Systems are provided for a three dimension static random access memory (SRAM) structure. The SRAM structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs extending vertically from a memory cell in a first memory array layer to a memory cell in a second memory array layer. The layer decoder circuitry on each memory array layer is configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to memory cells on its memory array layer. The word line driver circuit disposed on each memory array layer is configured to operate cooperatively with a partial SRAM address decoder to select and drive one of the plurality of word lines disposed on its memory array layer, wherein a selected word line is connected to a predetermined number of memory cells in a specific memory array layer.Type: ApplicationFiled: January 9, 2018Publication date: May 10, 2018Inventors: Chien-Yuan Chen, Chien-Yu Huang, Hau-Tai Shieh
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Patent number: 9941287Abstract: Systems and methods are provided for fabricating a static random access memory (SRAM) cell in a multi-layer semiconductor device structure. An example SRAM device includes a first array of SRAM cells, a second array of SRAM cells, a processing component, and one or more inter-layer connection structures. The first array of SRAM cells are formed in a first device layer of a multi-layer semiconductor device structure. The second array of SRAM cells are formed in a second device layer of the multi-layer semiconductor device structure, the second device layer being formed on the first device layer. The processing component is configured to process one or more input signals and generate one or more access signals. One or more inter-layer connection structures are configured to transmit the one or more access signals to activate the first device layer or the second device layer for allowing access to a target SRAM cell.Type: GrantFiled: January 20, 2017Date of Patent: April 10, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Yu Huang, Chien-Yuan Chen, Hau-Tai Shieh
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Patent number: 9875789Abstract: Systems are provided for a three dimension static random access memory (SRAM) structure. The SRAM structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs extending vertically from a memory cell in a first memory array layer to a memory cell in a second memory array layer. The layer decoder circuitry on each memory array layer is configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to memory cells on its memory array layer. The word line driver circuit disposed on each memory array layer is configured to operate cooperatively with a partial SRAM address decoder to select and drive one of the plurality of word lines disposed on its memory array layer, wherein a selected word line is connected to a predetermined number of memory cells in a specific memory array layer.Type: GrantFiled: November 22, 2013Date of Patent: January 23, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Yuan Chen, Chien-Yu Huang, Hau-Tai Shieh
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Publication number: 20170133387Abstract: Systems and methods are provided for fabricating a static random access memory (SRAM) cell in a multi-layer semiconductor device structure. An example SRAM device includes a first array of SRAM cells, a second array of SRAM cells, a processing component, and one or more inter-layer connection structures. The first array of SRAM cells are formed in a first device layer of a multi-layer semiconductor device structure. The second array of SRAM cells are formed in a second device layer of the multi-layer semiconductor device structure, the second device layer being formed on the first device layer. The processing component is configured to process one or more input signals and generate one or more access signals. One or more inter-layer connection structures are configured to transmit the one or more access signals to activate the first device layer or the second device layer for allowing access to a target SRAM cell.Type: ApplicationFiled: January 20, 2017Publication date: May 11, 2017Inventors: Chien-Yu Huang, Chien-Yuan Chen, Hau-Tai Shieh
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Patent number: 9558791Abstract: Systems and methods are provided for fabricating a static random access memory (SRAM) cell in a multi-layer semiconductor device structure. An example SRAM device includes a first array of SRAM cells, a second array of SRAM cells, a processing component, and one or more inter-layer connection structures. The first array of SRAM cells are formed in a first device layer of a multi-layer semiconductor device structure. The second array of SRAM cells are formed in a second device layer of the multi-layer semiconductor device structure, the second device layer being formed on the first device layer. The processing component is configured to process one or more input signals and generate one or more access signals. One or more inter-layer connection structures are configured to transmit the one or more access signals to activate the first device layer or the second device layer for allowing access to a target SRAM cell.Type: GrantFiled: December 5, 2013Date of Patent: January 31, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chien-Yu Huang, Chien-Yuan Chen, Hau-Tai Shieh
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Patent number: 9413318Abstract: The present invention discloses an audio playing system for protecting a storage medium of an electrical device. The audio playing system includes a detecting unit, a processing unit, an adjusting module and a playing module. The detecting unit detects vibration of the electrical device to generate a detection signal corresponding to the vibration. The processing unit compares the detection signal with the tolerable vibration value of the storage medium to generate a comparison result, and generates an adjustment signal according to the comparison result. The adjusting module adjusts an audio file according to the adjustment signal to generate an adjusted audio file. The playing module plays the adjusted audio file. The present invention also discloses an audio playing method for protecting a storage medium of an electrical device.Type: GrantFiled: June 14, 2013Date of Patent: August 9, 2016Assignee: COMPAL ELECTRONICS, INC.Inventors: Chien-Yu Huang, Po-Jung Chen, Shih-Hsuan Huang
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Publication number: 20150162052Abstract: Systems and methods are provided for fabricating a static random access memory (SRAM) cell in a multi-layer semiconductor device structure. An example SRAM device includes a first array of SRAM cells, a second array of SRAM cells, a processing component, and one or more inter-layer connection structures. The first array of SRAM cells are formed in a first device layer of a multi-layer semiconductor device structure. The second array of SRAM cells are formed in a second device layer of the multi-layer semiconductor device structure, the second device layer being formed on the first device layer. The processing component is configured to process one or more input signals and generate one or more access signals. One or more inter-layer connection structures are configured to transmit the one or more access signals to activate the first device layer or the second device layer for allowing access to a target SRAM cell.Type: ApplicationFiled: December 5, 2013Publication date: June 11, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: CHIEN-YU HUANG, CHIEN-YUAN CHEN, HAU-TAI SHIEH
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Publication number: 20150146480Abstract: Systems are provided for a three dimension static random access memory (SRAM) structure. The SRAM structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs extending vertically from a memory cell in a first memory array layer to a memory cell in a second memory array layer. The layer decoder circuitry on each memory array layer is configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to memory cells on its memory array layer. The word line driver circuit disposed on each memory array layer is configured to operate cooperatively with a partial SRAM address decoder to select and drive one of the plurality of word lines disposed on its memory array layer, wherein a selected word line is connected to a predetermined number of memory cells in a specific memory array layer.Type: ApplicationFiled: November 22, 2013Publication date: May 28, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: CHIEN-YUAN CHEN, CHIEN-YU HUANG, HAU-TAI SHIEH
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Patent number: 9001546Abstract: Disclosed is a novel static random access memory (SRAM) device. The SRAM device comprises a plurality of memory array layers vertically disposed one above another, a layer decoder circuit disposed on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs wherein each complementary bit line pair extends vertically to couple a memory cell in each memory array layer. Each memory array layer comprises a plurality of memory cells and a word line disposed thereon. Each word line is connected to the plurality of memory cells disposed on its memory array layer. The number of memory cells in a layer corresponds to a predetermined memory page size. Each layer decoder circuit is configured to decode a portion of an SRAM address to select its memory array layer if the SRAM address corresponds to memory cells on its memory array layer. Each word line driver circuit is configured to drive the word line disposed on its memory array layer.Type: GrantFiled: August 22, 2013Date of Patent: April 7, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chien-Yuan Chen, Chien-Yu Huang, Hau-Tai Shieh