Patents by Inventor Chien-Yuan Huang
Chien-Yuan Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12300575Abstract: A device includes a first semiconductor device including a first bonding layer; a second semiconductor device bonded to the first bonding layer of the first semiconductor device; thermal structures disposed beside the second semiconductor device and on the first bonding layer, wherein the thermal structures include a conductive material, wherein the thermal structures are electrically isolated from the first semiconductor device and from the second semiconductor device; an encapsulant disposed on the first bonding layer, wherein the encapsulant surrounds the second semiconductor device and surrounds the thermal structures; and a second bonding layer disposed over the encapsulant, the thermal structures, and the second semiconductor device.Type: GrantFiled: May 2, 2022Date of Patent: May 13, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Hua Yu, Chuei-Tang Wang, Shih-Chang Ku, Chien-Yuan Huang
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Publication number: 20250106187Abstract: A method, a network device, and a non-transitory computer-readable storage medium are described in relation to a low latency, low loss, and scalable throughput (LI4S)-triggered prioritized connection service. The LI4S-triggered prioritized connection service may enable an evolved packet data gateway (ePDG) to provision prioritized and non-prioritized tunnels with end devices via untrusted wireless local area networks. The prioritized tunnel may support LI4S or another quality of service in which the ePDG may provide prioritized data forwarding. The end device may transmit a request that includes priority data.Type: ApplicationFiled: September 22, 2023Publication date: March 27, 2025Inventors: Chien-Yuan Huang, Suzann Hua, Tony Ferreira
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Publication number: 20250069980Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.Type: ApplicationFiled: November 14, 2024Publication date: February 27, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wensen Hung, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Yu Chen, Tsung-Shu Lin, Chien-Yuan Huang, Chen-Hsiang Lao
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Publication number: 20250052963Abstract: A method for forming an optical device structure is provided. The method includes disposing a first end portion of an optical fiber into a fiber array unit structure. The first end portion penetrates through the fiber array unit structure. The method includes bonding the first end portion of the optical fiber to a co-packaged optical device. The method includes bonding a fiber shield structure to the fiber array unit structure and the co-packaged optical device after the first end portion is bonded to the co-packaged optical device. The fiber shield structure surrounds the optical fiber.Type: ApplicationFiled: August 7, 2023Publication date: February 13, 2025Inventors: Chien-Yuan HUANG, Shih-Chang KU, Chen-Hua YU, Chuei-Tang WANG
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Publication number: 20250008372Abstract: A method may include establishing, for a user equipment (UE) device, a data session via a network and determining whether the network is congested or overloaded. The method may also include instructing the UE device to re-register for a Category M1 (Cat-M1) data session, in response to determining that the network is congested or overloaded.Type: ApplicationFiled: June 29, 2023Publication date: January 2, 2025Inventors: Suzann Hua, Ratul K. Guha, Ye Huang, Chien-Yuan Huang
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Publication number: 20240430966Abstract: Systems and methods described herein enable 5G core session management function (SMF)/user plan function (UPF) relocation to support ATSSS-enabled evolved packet data gateways (ePDG). An ePDG receives an access traffic steering, switching and splitting (ATSSS) trigger message from a user equipment (UE) device. The UE device is connected via a first session using a session management function (SMF) and a via a second session using a packet data network gateway (PGW). The ATSSS trigger message includes an SMF identifier for the SMF. The ePDG sends, in response to the ATSSS trigger message, a request to the SMF to merge the first session and the second session into a single registration.Type: ApplicationFiled: June 26, 2023Publication date: December 26, 2024Inventors: Chien-Yuan Huang, Suzann Hua, Amir Hossein Khastoo
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Patent number: 12170237Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.Type: GrantFiled: June 14, 2023Date of Patent: December 17, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wensen Hung, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Yu Chen, Tsung-Shu Lin, Chien-Yuan Huang, Chen-Hsiang Lao
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Publication number: 20240379601Abstract: An integrated circuit package includes first and second dies bonded to each other. The first die includes first die pads over a first device, first bonding pads over the first die pads, a first conductive via disposed between and electrically connected to a first one of the first die pads and a first one of the first bonding pads, and a first thermal via disposed between a second one of the first die pads and a second one of the first bonding pads and electrically insulated from the second one of the first die pads or the second one of the first bonding pads. The second die includes second bonding pads. The first one of the first bonding pads is connected to a first one of the second bonding pads. The second one of the first bonding pads is connected to a second one of the second bonding pads.Type: ApplicationFiled: July 23, 2024Publication date: November 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Yuan Huang, Shih-Chang Ku, Chuei-Tang Wang, Chen-Hua Yu
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Publication number: 20240371828Abstract: Disclosed are a semiconductor stack structure and a manufacturing method of a semiconductor stack structure. In one embodiment, the semiconductor stack structure includes a first semiconductor element, a second semiconductor element side-by-side bonded to the first semiconductor element through a direct bonding manner and a third semiconductor element, wherein the first semiconductor element and the second semiconductor element are bonded on the third semiconductor element.Type: ApplicationFiled: July 15, 2024Publication date: November 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuei-Tang WANG, Chien-Yuan Huang, Shih-Chang Ku
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Publication number: 20240363547Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a chip package over and electrically connected to the wiring substrate. The chip package structure includes a first anti-warpage structure bonded to the wiring substrate. The first anti-warpage structure is made of a semiconductor material and electrically insulated from a wiring structure of the wiring substrate and the chip package. The chip package structure includes a heat dissipation structure over the wiring substrate and surrounding the chip package and the first anti-warpage structure.Type: ApplicationFiled: April 28, 2023Publication date: October 31, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Yuan HUANG, Chuei-Tang Wang, Shih-Chang Ku
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Patent number: 12125812Abstract: An integrated circuit package includes first and second dies bonded to each other. The first die includes first die pads over a first device, first bonding pads over the first die pads, a first conductive via disposed between and electrically connected to a first one of the first die pads and a first one of the first bonding pads, and a first thermal via disposed between a second one of the first die pads and a second one of the first bonding pads and electrically insulated from the second one of the first die pads or the second one of the first bonding pads. The second die includes second bonding pads. The first one of the first bonding pads is connected to a first one of the second bonding pads. The second one of the first bonding pads is connected to a second one of the second bonding pads.Type: GrantFiled: February 22, 2022Date of Patent: October 22, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Yuan Huang, Shih-Chang Ku, Chuei-Tang Wang, Chen-Hua Yu
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Patent number: 12125824Abstract: Disclosed are a semiconductor stack structure and a manufacturing method of a semiconductor stack structure. In one embodiment, the semiconductor stack structure includes a first semiconductor element, a second semiconductor element side-by-side bonded to the first semiconductor element through a direct bonding manner and a third semiconductor element, wherein the first semiconductor element and the second semiconductor element are bonded on the third semiconductor element.Type: GrantFiled: June 30, 2022Date of Patent: October 22, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuei-Tang Wang, Chien-Yuan Huang, Shih-Chang Ku
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Patent number: 12051668Abstract: A method of forming a semiconductor device includes applying an adhesive material in a first region of an upper surface of a substrate, where applying the adhesive material includes: applying a first adhesive material at first locations of the first region; and applying a second adhesive material at second locations of the first region, the second adhesive material having a different material composition from the first adhesive material. The method further includes attaching a ring to the upper surface of the substrate using the adhesive material applied on the upper surface of the substrate, where the adhesive material is between the ring and the substrate after the ring is attached.Type: GrantFiled: May 26, 2023Date of Patent: July 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuan-Yu Huang, Li-Chung Kuo, Sung-Hui Huang, Shang-Yun Hou, Tsung-Yu Chen, Chien-Yuan Huang
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Patent number: 12002721Abstract: A method of fabricating a semiconductor structure includes providing a first substrate comprising a first side and a second side opposite to the first side. A package is attached to the first side of the first substrate. A second substrate is attached to the second side of the first substrate. A plurality of electrical connectors is bonded between the second side of the first substrate and the second substrate. A lid is attached to the first substrate and the second substrate. The lid includes a ring part and a plurality of overhang parts. The ring part is over the first side of the first substrate. The plurality of overhang parts extends from corner sidewalls of the ring part toward the second substrate. The plurality of overhang parts are laterally aside the plurality of electrical connectors.Type: GrantFiled: July 27, 2022Date of Patent: June 4, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou, Chien-Yuan Huang
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Publication number: 20240096719Abstract: A semiconductor device includes a first substrate, an electronic component, and a lid. The first substrate includes a first substrate top side, a first substrate bottom side opposite to the first substrate top side, a first substrate lateral side interposed between the first substrate top side and the first substrate bottom side, and a connector structure. The electronic component is coupled to the first substrate top side and coupled to the connector structure. The lid includes a wall part including a ring part coupled to the first substrate top side, a first part of an overhang part coupled to the first substrate lateral side, and a second part of the overhang part extending from the first part of the overhang part away from the first substrate lateral side.Type: ApplicationFiled: November 22, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou, Chien-Yuan Huang
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Publication number: 20240056803Abstract: A device establishes a first encrypted tunnel with a first active security gateway at a first data center to enable the device to communicate, via the first encrypted tunnel, with a first access and mobility management function (AMF) at the first data center. The device forwards, via the first encrypted tunnel and the first active security gateway, a first User Equipment device (UE) message to the first AMF. The device determines an occurrence of a failure or overload condition at the first active security gateway, and establishes, based on the determined occurrence of the failure or overload condition, a second encrypted tunnel with a standby security gateway at a second data center to enable the device to communicate, via the second encrypted tunnel, with the first AMF. The device forwards, via the second encrypted tunnel and the standby security gateway, at least one second UE message to the first AMF.Type: ApplicationFiled: August 9, 2022Publication date: February 15, 2024Inventors: Chien-Yuan Huang, Suzann Hua, Helen Osias Eglip, Parry Cornell Booker
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Patent number: 11889568Abstract: A device may include a processor configured to detect that an Internet Protocol Security (IPsec) tunnel from a user equipment (UE) device connected via a WiFi connection has become idle, based on the IPsec tunnel meeting an idleness criterion, and instruct the UE device to tear down the IPsec tunnel, in response to detecting that the IPsec tunnel from the UE device connected via the WiFi connection meets the idleness criterion. The device may be further configured to receive a mobile terminating call for the UE device; establish a new IPsec tunnel to the UE device via the WiFi connection, in response to receiving the mobile terminating call for the UE device; and forward the received mobile terminating call to the UE device via the established new IPsec tunnel.Type: GrantFiled: September 22, 2022Date of Patent: January 30, 2024Assignee: Verizon Patent and Licensing Inc.Inventors: Chien-Yuan Huang, Suzann Hua, Parry Cornell Booker
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Publication number: 20240030099Abstract: Disclosed are a semiconductor structure and a manufacturing method of a semiconductor structure. In one embodiment, the semiconductor structure includes a first semiconductor element, a second semiconductor element, a heat dissipation element and a gap-filling material. The second semiconductor element is on the first semiconductor element. The heat dissipation element is on the first semiconductor element and spaced apart from the second semiconductor element by a gap. The gap-filling material is filled in the gap between the second semiconductor element and the heat dissipation element.Type: ApplicationFiled: July 19, 2022Publication date: January 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuei-Tang Wang, Chien-Yuan Huang, Shih-Chang Ku
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Publication number: 20240006379Abstract: Disclosed are a semiconductor stack structure and a manufacturing method of a semiconductor stack structure. In one embodiment, the semiconductor stack structure includes a first semiconductor element, a second semiconductor element side-by-side bonded to the first semiconductor element through a direct bonding manner and a third semiconductor element, wherein the first semiconductor element and the second semiconductor element are bonded on the third semiconductor element.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuei-Tang Wang, Chien-Yuan Huang, Shih-Chang Ku
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Patent number: 11849321Abstract: Systems and method are provided for a temporary network slice usage barring service within a core network. A network device in the core network receives a slice barring information message for an application function (AF). The slice barring information message includes a unique subscriber identifier associated with a user equipment (UE) device to be barred from a network slice and indicates a barring expiration time. The network device stores barring parameters based on the slice barring information message. The barring parameters include a slice identifier associated with the AF, the unique subscriber identifier, and the barring expiration time. The network device sends a barring instruction message to another network device associated with the network slice. The barring instruction message includes the unique subscriber identifier and the barring expiration time. The other network device enforces temporary barring of the UE device from the network slice based on the barring instruction message.Type: GrantFiled: May 20, 2022Date of Patent: December 19, 2023Assignee: Verizon Patent and Licensing Inc.Inventors: Suzann Hua, Ye Huang, Chien-Yuan Huang, Parry Cornell Booker