Abstract: Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.

Abstract: A method of making a semiconductor device includes forming a circuit layer over a substrate. The method further includes depositing an insulator over the substrate. The method further includes patterning the insulator to define a test line trench, a first trench, and a second trench, wherein the first trench is on a portion of the substrate exposed by the circuit layer. The method further includes filling the test line trench to define a test line electrically connected to the circuit layer. The method further includes filling the first trench and the second trench to define a capacitor.

Abstract: A semiconductor device includes a first substrate, an electronic component, and a lid. The first substrate includes a first substrate top side, a first substrate bottom side opposite to the first substrate top side, a first substrate lateral side interposed between the first substrate top side and the first substrate bottom side, and a connector structure. The electronic component is coupled to the first substrate top side and coupled to the connector structure. The lid includes a wall part including a ring part coupled to the first substrate top side, a first part of an overhang part coupled to the first substrate lateral side, and a second part of the overhang part extending from the first part of the overhang part away from the first substrate lateral side.

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.

Abstract: A method of using NC-MRA to generate pelvic veins images and measure rate of blood flow includes subjecting a lay patient to undergo magnetic resonance scan in cooperation with an ECG monitor and a respiration monitor; scanning coronary sections and transverse sections of kidney veins, lower cavity veins, common iliac veins, and external iliac veins to generate two-dimensional images wherein the two-dimensional images use balanced turbo field echo wave sequence; scanning coronary sections of common cardinal veins of abdominal cavity to generate three-dimensional images wherein the three-dimensional images use fast spin-echo short tau inversion recovery wave sequence and sample signals when the ECG monitor monitors myocardial contractility; and using quantification phase-contrast analysis to measure blood flowing through the transverse sections of the veins in a two-dimensional scan.

Abstract: A device establishes a first encrypted tunnel with a first active security gateway at a first data center to enable the device to communicate, via the first encrypted tunnel, with a first access and mobility management function (AMF) at the first data center. The device forwards, via the first encrypted tunnel and the first active security gateway, a first User Equipment device (UE) message to the first AMF. The device determines an occurrence of a failure or overload condition at the first active security gateway, and establishes, based on the determined occurrence of the failure or overload condition, a second encrypted tunnel with a standby security gateway at a second data center to enable the device to communicate, via the second encrypted tunnel, with the first AMF. The device forwards, via the second encrypted tunnel and the standby security gateway, at least one second UE message to the first AMF.

Abstract: A device may include a processor configured to detect that an Internet Protocol Security (IPsec) tunnel from a user equipment (UE) device connected via a WiFi connection has become idle, based on the IPsec tunnel meeting an idleness criterion, and instruct the UE device to tear down the IPsec tunnel, in response to detecting that the IPsec tunnel from the UE device connected via the WiFi connection meets the idleness criterion. The device may be further configured to receive a mobile terminating call for the UE device; establish a new IPsec tunnel to the UE device via the WiFi connection, in response to receiving the mobile terminating call for the UE device; and forward the received mobile terminating call to the UE device via the established new IPsec tunnel.

Abstract: Disclosed are a semiconductor structure and a manufacturing method of a semiconductor structure. In one embodiment, the semiconductor structure includes a first semiconductor element, a second semiconductor element, a heat dissipation element and a gap-filling material. The second semiconductor element is on the first semiconductor element. The heat dissipation element is on the first semiconductor element and spaced apart from the second semiconductor element by a gap. The gap-filling material is filled in the gap between the second semiconductor element and the heat dissipation element.

Abstract: Disclosed are a semiconductor stack structure and a manufacturing method of a semiconductor stack structure. In one embodiment, the semiconductor stack structure includes a first semiconductor element, a second semiconductor element side-by-side bonded to the first semiconductor element through a direct bonding manner and a third semiconductor element, wherein the first semiconductor element and the second semiconductor element are bonded on the third semiconductor element.

Abstract: Systems and method are provided for a temporary network slice usage barring service within a core network. A network device in the core network receives a slice barring information message for an application function (AF). The slice barring information message includes a unique subscriber identifier associated with a user equipment (UE) device to be barred from a network slice and indicates a barring expiration time. The network device stores barring parameters based on the slice barring information message. The barring parameters include a slice identifier associated with the AF, the unique subscriber identifier, and the barring expiration time. The network device sends a barring instruction message to another network device associated with the network slice. The barring instruction message includes the unique subscriber identifier and the barring expiration time. The other network device enforces temporary barring of the UE device from the network slice based on the barring instruction message.

Abstract: A method, a device, and a non-transitory storage medium are described in which an capacity modification service is provided in relation to a virtual device. The capacity modification service may include a first virtual device of a host device that is able to a receive resource modification request directed to a second virtual device of the host device. The modification request may be received via user interface or application programming interface associated with the first and second virtual devices. The first virtual device may calculate resource values for resources of the prospective resource modification. The first virtual device may communicate the resource values to management layer of the host device, such as a container orchestrator. The container orchestrator may allocate the resources for the second virtual device based on the resource values.

Abstract: A device includes a first semiconductor device including a first bonding layer; a second semiconductor device bonded to the first bonding layer of the first semiconductor device; thermal structures disposed beside the second semiconductor device and on the first bonding layer, wherein the thermal structures include a conductive material, wherein the thermal structures are electrically isolated from the first semiconductor device and from the second semiconductor device; an encapsulant disposed on the first bonding layer, wherein the encapsulant surrounds the second semiconductor device and surrounds the thermal structures; and a second bonding layer disposed over the encapsulant, the thermal structures, and the second semiconductor device.

Abstract: An anti-collision mechanism comprises a body, a collision baffle, a magnetic element, and a magnetic field sensor, and the anti-collision mechanism is configured to be applicable to a sweeping robot. The magnetic field sensor is arranged at a distance from the magnetic element, the magnetic field sensor is configured to detect a change in the magnetic field intensity caused by a change in the distance between the magnetic field sensor and the magnetic element. When the collision occurs, the magnetic element is closer to the magnetic field sensor to make the magnetic field intensity change, thus generating signals to stop or turn the sweeping robot, which can realize the obstacle avoidance of the sweeping robot and enhance the service life. The sweeping robot is also provided.

Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.

Abstract: A method of forming a semiconductor device includes applying an adhesive material in a first region of an upper surface of a substrate, where applying the adhesive material includes: applying a first adhesive material at first locations of the first region; and applying a second adhesive material at second locations of the first region, the second adhesive material having a different material composition from the first adhesive material. The method further includes attaching a ring to the upper surface of the substrate using the adhesive material applied on the upper surface of the substrate, where the adhesive material is between the ring and the substrate after the ring is attached.

Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a lid and outer flanges. The lid overlies the semiconductor package. The outer flanges are disposed at edges of the lid, are connected with the lid, extend from the lid towards the circuit substrate, and face side surfaces of the semiconductor package. The lid has a first region that is located over the semiconductor package and is thicker than a second region that is located outside a footprint of the semiconductor package.

Abstract: Systems and methods described herein include receiving, from a first network function, a request to receive a notification when a second network function becomes available after a failure. A status update may be received from the second network function indicating that the second network function is available. It may be determined that the second network function is in a stable state. A notification may be sent, to the first network function, that the second network function is available along with an indication of a time period in which to switch from accessing a third network function to accessing the second network function.

Abstract: A method of forming a semiconductor device includes applying an adhesive material in a first region of an upper surface of a substrate, where applying the adhesive material includes: applying a first adhesive material at first locations of the first region; and applying a second adhesive material at second locations of the first region, the second adhesive material having a different material composition from the first adhesive material. The method further includes attaching a ring to the upper surface of the substrate using the adhesive material applied on the upper surface of the substrate, where the adhesive material is between the ring and the substrate after the ring is attached.

Abstract: A method includes forming a first dielectric layer on a first wafer, and forming a first bond pad penetrating through the first dielectric layer. The first wafer includes a first semiconductor substrate, and the first bond pad is in contact with a first surface of the first semiconductor substrate. The method further includes forming a second dielectric layer on a second wafer and forming a second bond pad extending into the second dielectric layer. The second wafer includes a second semiconductor substrate. The first wafer is sawed into a plurality of dies, with the first bond pad being in a first die in the plurality of dies. The first bond pad is bonded to the second bond pad.

Abstract: A semiconductor structure includes a first die, second dies coupled to and on the first die, a dielectric layer on the first die and covering each second die, and through dielectric vias (TDVs) coupled to and on the first die. The first die includes a bonding dielectric layer and bonding features embedded in and leveled with the bonding dielectric layer. An array of second dies is arranged in a first region of the first die. Each second die includes a bonding dielectric layer and a bonding feature embedded in and leveled with the bonding dielectric layer. The bonding dielectric layer and the bonding feature of each second die are respectively bonded to those of the first die. The TDVs are laterally covered by the dielectric layer in a second region of the first die which is connected to the first region and arranged along a periphery of the first die.