Abstract: A wireless charging receiver that includes a first coil, a second coil, and a nanocrystalline sheet is disclosed. The first coil is configured to be located within a recess in the nanocrystalline sheet and is positioned between the second coil and the nanocrystalline sheet. The first coil includes first and second terminals and the second coil includes third and fourth terminals. The first terminal is connected to the third terminal and the second terminal is connected to the fourth terminal to electrically connect the first coil to the second coil. The first coil may be formed of a flexible printed circuit board having a continuous trace or may be formed of litz wire. The first coil may be a hybrid coil with a first portion formed of a flexible printed circuit board having a continuous trace and with a second portion formed of litz wire.

Abstract: A semiconductor device includes a first semiconductor fin that is formed over a substrate and extends along a first lateral axis. The semiconductor device includes a second semiconductor fin that is also formed over the substrate and extends along the first lateral axis. At least a tip portion of the first semiconductor fin and at least a tip portion of the second semiconductor fin bend toward each other along a second lateral axis that is perpendicular to the first lateral axis.

Abstract: An electronic device having a first area and a second area adjacent to the first area is provided, which includes a flexible substrate, a first conductive layer disposed on the flexible substrate and in the first area and the second area, a semiconductor disposed on the flexible substrate and electrically connected to the first conductive layer, a second conductive layer disposed on the first conductive layer, and an organic layer disposed on the first conductive layer and in the first area and the second area. The second conductive layer has a first portion and a second portion are respectively contacted the first conductive layer in the first area. In a cross-sectional view, a first portion of the organic layer is directly contacted the first conductive layer and the second conductive layer and disposed between the first portion and the second portion of the second conductive layer.

Abstract: A power converter is provided. The power converter includes first to fourth switches electrically connected in series, a flying capacitor and a controller. Positive and negative terminals of the flying capacitor are electrically connected to the second and third switches respectively. The controller operates the first and fourth switches to perform a first complementary switching with a first dead time, and operates the second and third switches to perform a second complementary switching with a second dead time. The controller determines to regulate the first or second dead time by detecting a capacitor voltage of the flying capacitor, such that the capacitor voltage of the flying capacitor is maintained within a balance voltage range.

Abstract: A method includes moving a wafer transport device on a transport rail, wherein the wafer transport device comprises a hoist unit configured to grip a wafer container unit; stopping the wafer transport device above a load port; after stopping the wafer transport device, reading data of a rail mark located on the transport rail; aligning an orientation of the wafer transport device according to the data of the rail mark; after aligning the orientation of the wafer transport device according to the data of the rail mark, aligning the wafer transport device with respect to a top surface of the load port; after aligning the wafer transport device with respect to the top surface of the load port, lowering the hoist unit.

Abstract: In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor substrate includes a semiconductor material over a base substrate. The semiconductor substrate has one or more sidewalls forming a crack stop trench that is laterally between a central region of the semiconductor substrate and a peripheral region of the semiconductor substrate that surrounds the central region. The peripheral region of the semiconductor substrate includes a plurality of cracks.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) chip comprising a front-end-of-line (FEOL) through semiconductor-on-substrate via (TSV), as well as a method for forming the IC chip. In some embodiments, a semiconductor layer overlies a substrate. The semiconductor layer may, for example, be or comprise a group III-V semiconductor and/or some other suitable semiconductor(s). A semiconductor device is on the semiconductor layer, and a FEOL layer overlies the semiconductor device. The FEOL TSV extends through the FEOL layer and the semiconductor layer to the substrate at a periphery of the IC chip. An intermetal dielectric (IMD) layer overlies the FEOL TSV and the FEOL layer, and an alternating stack of wires and vias is in the IMD layer.

Abstract: A signal processing circuit, complying with DisplayPort standard and operated in a display device which is as a DisplayPort sink device, includes a main physical circuit, which is configured to receive a first signal from one of a plurality of DisplayPort connectors of the display device connected to a first DisplayPort source device and a plurality of auxiliary physical circuits. Only a first auxiliary physical circuit of the plurality of auxiliary physical circuits is enabled to receive a second signal from the DisplayPort connector connected to the first DisplayPort source device.

Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a source/drain region disposed over a substrate, a first interlayer dielectric layer surrounding a first portion of the source/drain region, a second interlayer dielectric layer distinct from the first interlayer dielectric layer surrounding a second portion of the source/drain region, a silicide layer disposed on the source/drain region, and a conductive contact disposed over the source/drain region. The conductive contact is disposed in the second interlayer dielectric layer.

Abstract: A passivation layer and conductive via are provided, wherein the transmittance of an imaging energy is increased within the material of the passivation layer. The increase in transmittance allows for a greater cross-linking that helps to increase control over the contours of openings formed within the passivation layer. Once the openings are formed, the conductive vias can be formed within the openings.

Abstract: An air-floating guide rail device includes a guide rail unit, a slider unit, and a linear motor unit. The guide rail unit includes a guide rail body and two air-floating block sets made of a material different from that of the guide rail body and each including top and side air-floating blocks. The slider unit includes a main sliding seat and two lateral sliding seats connected integrally to the main sliding seat and each having first and second guiding surfaces transverse to each other and disposed respectively adjacent to corresponding top and side air-floating blocks, and first and second air guiding passages connecting the first and second guiding surfaces to the external environment. The linear motor unit includes a stator and a mover mounted fixedly to the main sliding seat and movable relative to the stator for driving linear movement of the slider unit relative to the guide rail unit.

Abstract: A wavelength conversion module includes a driving assembly, a wavelength conversion substrate, and a clamping element. The driving assembly is connected to the wavelength conversion substrate to drive the wavelength conversion substrate to rotate around a central axis of the driving assembly. The clamping element is attached to the wavelength conversion substrate along the central axis. At least one of the wavelength conversion substrate and the clamping element includes at least one recess and at least one through hole. A direction of the through hole is parallel to the central axis, and the clamping element, the recess, and the wavelength conversion substrate define at least one heat dissipation channel. The through hole is relatively adjacent to the central axis and is in communication with the heat dissipation channel.

Abstract: A device includes a gate stack and a channel layer over the gate stack. The gate stack includes a metal gate electrode, a ferroelectric layer, and a semiconducting oxide layer disposed between the ferroelectric layer and the metal gate electrode. The semiconducting oxide layer has a thickness between approximately 1 ?m and approximately 30 ?m.

Abstract: A display control chip includes a first memory and a computing circuit. The first memory is configured to store a plurality of chart templates. The computing circuit is coupled with the first memory, is configured to receive first update data, and is configured to use the first update data to update raw data in a second memory. When the computing circuit reads the raw data in the second memory, the computing circuit is configured to: determine a target chart template of the plurality of chart templates, according to the first update data; convert the raw data into a chart image, according to the target chart template; and output first display data according to the chart image, in which the first display data is for generating a first display picture including the chart image.

Abstract: A display control chip comprises a computing circuit and an on-screen display (OSD) buffer. The computing circuit is configured to receive update data, and is configured to use the update data to update animation data in a memory. The animation data comprises a plurality of images. The OSD buffer is coupled with the computing circuit. When the computing circuit reads the animation data in the memory, the computing circuit is configured to sequentially write the plurality of images into the OSD buffer. The OSD buffer is configured to sequentially output the plurality of images to a display circuit to form an OSD animation on the display circuit.

Abstract: The present disclosure describes a wafer cooling/heating system that includes a load-lock and a thermo module. The load-lock uses a level stream design to improve temperature uniformity across one or more wafers during a cooling/heating process. The load-lock can include (i) a wafer holder configured to receive wafers at a front side of the load-lock; (ii) a gas diffuser with one or more nozzles along a back side of the load-lock, a side surface of the load-lock, or a combination thereof; and (iii) one or more exhaust lines. Further, the thermo module can be configured to control a temperature of a gas provided to the load-lock.

Abstract: A display control chip includes a first memory and a computing circuit. The first memory is configured to store a plurality of character images respectively corresponds to a plurality of characters of a character encoding format. The computing circuit is coupled with the first memory, and is configured to receive first update data generated by encoding input data according to the character encoding format, and is configured to use the first update data to update text data in a second memory. When the computing circuit reads the text data in the second memory, the computing circuit is configured to: search among the plurality of character images to find a plurality of target images corresponding to the text data; and output first display data according to the plurality of target images, in which the first display data is for generating a first display picture including the plurality of target images.

Abstract: A memory device and an intelligent operation method thereof are provided. The memory device includes a memory array, a signal generating circuit, an environment detecting circuit and an artificial intelligence (AI) circuit. The signal generating circuit is configured to generate an inputting signal. The environment detecting circuit is configured to detect at least one environment information. The AI circuit is connected among the memory array, the signal generating circuit and the environment detecting circuit. The AI circuit at least receives the inputting signal from the signal generating circuit, receives the environment information from the environment detecting circuit, receives a first performance information from the memory array, receives a second performance information from the AI circuit and outputs an ideal signal to the memory array according to the inputting signal, the environment information, the first performance information and the second performance information.

Abstract: A method of forming a semiconductor device structure includes forming a first resist structure over a hard mask. The method further includes patterning the first resist structure to form a trench therein. The method further includes performing a first hydrogen plasma treatment to the patterned first resist structure, wherein the first hydrogen plasma treatment is configured to smooth sidewalls of the trench. The method further includes patterning the hard mask using the patterned resist structure as an etch mask. The method further includes forming a second resist structure over the patterned hard mask. The method further includes patterning the second resist structure to form an opening therein. The method further includes performing a second hydrogen plasma treatment to the patterned second resist structure. The method further includes patterning the patterned hard mask using the patterned second resist structure as a second etch mask.

Abstract: The image detecting apparatus including an image capturing device, a microphone array and a processing circuit is provided. The image capturing device captures an image. The microphone array detects a voice source. The processing circuit performs a voice activity detection on a first number of voice signals captured by the microphone devices to determine whether the voice source is a preset type voice. The processing circuit performs a beamforming operation on a second number of voice signals captured by the microphone devices to generate a region of interest (ROI) setting signal when the voice source is the preset type voice. The ROI setting signal indicates a location of the voice source in the image. The processing circuit performs an image detecting operation on a ROI image. The ROI image is determined according to the image and the ROI setting signal. The first number is smaller than the second number.