Patents by Inventor Chih-An Chen

Chih-An Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ELECTRONIC DEVICE
    Publication number: 20240224482
    Abstract: The present invention discloses an electronic device. The electronic device includes a connector and a sensing control unit. The connector includes a metal mask and at least one terminal. The sensing control unit is electrically connected to the metal mask and the at least one terminal. The sensing control unit is suitable for sensing whether the connector is connected to an external device, and includes a proximity sensing circuit connected to the metal mask. When the connector is connected to the external device, the sensing control unit enables the metal mask to be grounded. When the connector is not connected to the external device, the sensing control unit enables the metal mask to be floated, and the floated metal mask is suitable as a sensing electrode of the proximity sensing circuit.
    Type: Application
    Filed: October 10, 2023
    Publication date: July 4, 2024
    Inventors: Chun-Chih CHEN, Chien-Yi WU, Wei-Chieh CHIN, Cheng-Yu WEI, Chia-Ho TING, Huan-Li CHU
  • PACKAGE STRUCTURE COMPRISING BUFFER LAYER FOR REDUCING THERMAL STRESS AND METHOD OF FORMING THE SAME
    Publication number: 20240222215
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.
    Type: Application
    Filed: March 14, 2024
    Publication date: July 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Chien-Hsun Lee, Chung-Shi Liu, Hao-Cheng Hou, Hung-Jui Kuo, Jung-Wei Cheng, Tsung-Ding Wang, Yu-Hsiang Hu, Sih-Hao Liao
  • MAMMALIAN CELL LINE AND METHOD FOR PRODUCING SOLUBLE E2 RECOMBINANT ANTIGEN OF CLASSICAL SWINE FEVER VIRUS USING THE SAME AND APPLICATION THEREOF
    Publication number: 20240209033
    Abstract: The present disclosure relates to a mammalian cell line and a method for producing soluble E2 recombinant antigen of classical swine fever virus using the same. A mammalian cell expression system with different cell passage numbers can stably express a large amount of soluble CSFV-E2 recombinant protein, effectively reducing the production cost of CSFV-E2 recombinant protein, and then applied to the production of CSFV-E2 protein subunit vaccines.
    Type: Application
    Filed: October 12, 2023
    Publication date: June 27, 2024
    Applicant: National Pingtung University Of Science And Technology
    Inventors: Hso-Chi Chaung, Wen-Bin Chung, Chi-Chih Chen
  • METHOD FOR DECOLORIZING POLYESTER FABRIC AND POLYESTER FABRIC
    Publication number: 20240209569
    Abstract: A method for decolorizing polyester fabric and a polyester fabric are provided. The method for decolorizing polyester fabric includes providing a dye-attached polyester fabric. The dye-attached polyester fabric is immersed in a first solution, obtaining a treated polyester fabric. The treated polyester fabric is immersed in a second solution, to obtain a decolorized polyester fabric. The first solution includes water, a first swelling agent and a solubility promoter. The second solution includes water, a second swelling agent, and an auxiliary swelling agent.
    Type: Application
    Filed: April 19, 2023
    Publication date: June 27, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chung-Yang CHUANG, Chih-An CHEN, Min-Yan DONG, Chang-Jung CHANG, Hui-Min WANG
  • MULTIFUNCTIONAL PIPETTE AND AUTOMATIC DETECTION MACHINE
    Publication number: 20240207835
    Abstract: A multifunctional pipette includes a pipette module, a heater module and a magnetic module. The pipette module includes one or more pipette heads. The heater module has a first joint part, and the heater module configured to removably connect to the pipette module by coupling the first joint part to at least one of the plurality of pipette heads. The magnetic module has a second joint part, and the magnetic module configured to removably connect to the pipette module by coupling the second joint part to at least one of the plurality of pipette heads. The multifunctional pipette can be further applied in an automatic detection machine.
    Type: Application
    Filed: March 14, 2023
    Publication date: June 27, 2024
    Inventors: Chih-Chen CHANG, Chih-Ying CHU, Chih-Kuan LIN
  • Trench etching process for photoresist line roughness improvement
    Patent number: 12020933
    Abstract: A method of forming a semiconductor device structure includes forming a resist structure over a substrate, the resist structure includes an anti-reflective coating (ARC) layer and a photoresist layer over the ARC layer. The method further includes patterning the photoresist layer to form a trench therein. The method further includes performing a hydrogen plasma treatment to the patterned photoresist layer, wherein the hydrogen plasma treatment is configured to smooth sidewalls of the trench, and the hydrogen plasma treatment is performed at a temperature ranging from about 200° C. to about 600° C. The method further includes patterning the ARC layer using the patterned photoresist layer as a etch mask.
    Type: Grant
    Filed: November 10, 2022
    Date of Patent: June 25, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED
    Inventors: Sheng-Lin Hsieh, I-Chih Chen, Ching-Pei Hsieh, Kuan Jung Chen
  • DIE AND PACKAGE STRUCTURE
    Publication number: 20240203924
    Abstract: A die includes a substrate, a conductive pad, a connector a protection layer, and a passivation layer. The conductive pad is disposed over the substrate. The connector is disposed on the conductive pad. The connector comprises a seed layer and a conductive post on the seed layer. The protection layer laterally covers the connector. The passivation layer is disposed between the protection layer and the conductive pad. The conductive post is separated from the passivation layer and the protection layer by the seed layer.
    Type: Application
    Filed: March 5, 2024
    Publication date: June 20, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
  • SEMICONDUCTOR STRUCTURES AND METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE
    Publication number: 20240203848
    Abstract: The present application discloses a semiconductor structure and a method for manufacturing a semiconductor structure. The semiconductor structure includes at least one bottom die and a plurality of top dies. The semiconductor structure further includes a redistribution layer (RDL) formed on the at least one bottom die, and a plurality of micro bumps formed on the RDL. The top dies is stacked on the bottom die with their front sides being attached to the micro bumps. The RDL allows communication between a top die and the bottom die and allows the communication between adjacent top dies. The die-stacking structure enables greater computation capability within a smaller area.
    Type: Application
    Filed: March 31, 2023
    Publication date: June 20, 2024
    Inventors: TZU-WEI CHIU, CHUN-WEI CHANG, WEI-CHIH CHEN, CHE-YEN HUANG
  • SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGE
    Publication number: 20240203925
    Abstract: The present application discloses a semiconductor package and a method for manufacturing a semiconductor package. The semiconductor package includes a plurality of bottom dies and a plurality of top dies stacked on the bottom dies with a first RDL in between, thereby embedding more computation power within one semiconductor package and enabling flexible routing between dies. In addition, the top dies and the bottom dies are stacked in a face-to-face manner so the signal paths between the top dies and the bottom dies can be shortened, and thus, the IR drop of the transmission between dies can be reduced.
    Type: Application
    Filed: November 8, 2023
    Publication date: June 20, 2024
    Inventors: TZU-WEI CHIU, CHUN-WEI CHANG, WEI-CHIH CHEN, CHE-YEN HUANG
  • REVERSE BIAS FOR CORROSION PROTECTION IN LIQUID COOLING SYSTEMS
    Publication number: 20240206115
    Abstract: A liquid cooling system with a reverse bias system is described. The reverse bias system serves several functions, including monitoring a corrosion in the liquid cooling system as well as providing a reverse bias voltage to reduce a galvanic current in the system and to prevent corrosion in the liquid cooling system. The reverse bias system in the liquid cooling system allows for heterogeneous usage of metallic materials, which results in a lighter weight and easier to fabricate liquid cooling system.
    Type: Application
    Filed: December 16, 2022
    Publication date: June 20, 2024
    Inventors: Chun Chih CHEN, Vipulkumar K. PATEL
  • SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGE
    Publication number: 20240203941
    Abstract: The present application discloses a semiconductor package and a method for manufacturing the semiconductor package. The semiconductor package includes a first dielectric layer, a first redistribution layer (RDL) disposed on a first surface of the first dielectric layer, a first bonding layer disposed on the first RDL, a plurality of bottom dies attached to the first bonding layer, a second dielectric layer filling gaps between the bottom dies, a plurality of conductive pillars disposed in the second dielectric layer without contacting the bottom dies, a second RDL disposed on the second dielectric layer and the bottom dies, a second bonding layer disposed on the second RDL, a plurality of top dies attached to the second bonding layer, a third dielectric layer filling gaps between the top dies, and a plurality of solder bumps disposed on a second surface of the first dielectric layer.
    Type: Application
    Filed: December 12, 2023
    Publication date: June 20, 2024
    Inventors: TZU-WEI CHIU, CHUN-WEI CHANG, WEI-CHIH CHEN, CHE-YEN HUANG
  • Anti-tumor antigen nanobody and nucleic acid encoding sequence thereof, and uses of the same
    Patent number: 12012454
    Abstract: The present disclosure provides an anti-tumor antigen nanobody that specifically binds to a human leukocyte antigen-G. The present disclosure also provides the nucleic acid sequence of the anti-tumor antigen nanobody, use of the anti-tumor antigen nanobody for treating cancer and immune-related disorders, and a method for detecting expression levels of HLA-G.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: June 18, 2024
    Assignee: CHINA MEDICAL UNIVERSITY HOSPITAL
    Inventors: Der-Yang Cho, Shao-Chih Chiu, Shi-Wei Huang, Chih-Ming Pan, Mei-Chih Chen, Yu-Chuan Lin, Yeh Chen
  • PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME
    Publication number: 20240194569
    Abstract: A package structure and method of forming the same are provided. The package structure includes a die, a through via, an encapsulant, an adhesion promoter layer, an insulating layer and a polymer layer. The through via is laterally aside the die. The encapsulant laterally encapsulates the die and the a through via. The adhesion promoter layer and an insulating layer are sandwiched between the a through via and the encapsulant. Sidewalls of the a through via are covered by the adhesion promoter layer and the insulating layer. The polymer layer is located under the through via and encapsulant. The insulating layer includes a plurality of portions.
    Type: Application
    Filed: February 21, 2024
    Publication date: June 13, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chun Cho, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Wei-Chih Chen
  • Catalyst for methanation reaction and method for preparing methane
    Patent number: 12005427
    Abstract: A catalyst for methanation reaction and a method for preparing methane are provided. The catalyst for methanation reaction includes a core, a shell encapsulating the core, and an active metal. The core includes cerium dioxide (CeO2), the shell includes zirconium dioxide (ZrO2), and the active metal is in particle form and is disposed on an outer surface of the shell layer.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: June 11, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yen-Chih Chen, Man-Yin Lo, Hsi-Yen Hsu, Ying-Chieh Lee, Yuan-Peng Du
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20240186308
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a redistribution layer (RDL) module, a first semiconductor module, an interconnection module, a second semiconductor module and a molding material. The first semiconductor module is disposed on the RDL module. The interconnection module is disposed on the RDL module. The second semiconductor module is disposed on the interconnection module. The molding material covers the RDL module and surrounds the first semiconductor module and the second semiconductor module. A top surface of the first semiconductor module and a top surface of the second semiconductor module are exposed by the molding material.
    Type: Application
    Filed: January 19, 2023
    Publication date: June 6, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Fung CHANG, Chin-Wei LIANG, Sheng-Feng WENG, Ming-Yu YEN, CHEYU LIU, Hung-Chih CHEN, Yi-Yang LEI, CHING-HUA HSIEH, Hung-Chou LIAO
  • Rope based fall protection device
    Patent number: 11998776
    Abstract: A rope based fall protection device including a rotation unit, a brake unit, and a rope. A first end of the rope is connected to the rotation unit. The rope includes a first rope loop and a second rope loop that are wound around the rotation unit. A first retaining portion of a retaining ring is sleeved on the first rope loop and a second retaining portion thereof is sleeved on the second rope loop, such that the rope forms a rope section which has a fixed length between the second retaining portion and the first end and is wound around the rotation unit. When a free end of the rope is pulled by an external force to release the rope wound around the rotation unit in a direction away from the rotation unit, the retaining ring is broken to release the rope section of the rope. The external force is greater than or equal to a pulling force generated by a user's free fall.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: June 4, 2024
    Assignee: YOKE INDUSTRIAL CORP.
    Inventors: Wen-Ming Liao, Wei-Chih Chen
  • SEMICONDUCTOR DEVICE STRUCTURE INCLUDING FORKSHEET TRANSISTORS AND METHODS OF FORMING THE SAME
    Publication number: 20240178128
    Abstract: A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall. The structure also includes a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type. The structure further includes a gate bridge contact disposed on the first dielectric wall, and a gate via contact disposed on the gate bridge contact.
    Type: Application
    Filed: January 22, 2023
    Publication date: May 30, 2024
    Inventors: Hong-Chih CHEN, Chun-Sheng LIANG, Yu-San CHIEN, Wei-Chih KAO
  • MULTIPLE TRANSCEIVER COOLING SYSTEM
    Publication number: 20240178867
    Abstract: A multiple transceiver cooling system includes a networking device, a plurality of transceiver device chassis that are included in the networking device, that are positioned adjacent each other, and that are each configured to receive a respective transceiver device, and a multiple transceiver heat dissipation device that engages each of the plurality of transceiver device chassis. With the multiple transceiver heat dissipation device engaging each of the plurality of transceiver device chassis, the multiple transceiver heat dissipation device may receive heat generated by respective transceiver devices located in the plurality of transceiver device chassis, transfer the heat to a heat dissipation element, and dissipate the heat using the heat dissipation element.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 30, 2024
    Inventors: Yen-Chih Chen, Shih-Huai Cho
  • Wind chime
    Patent number: 11996072
    Abstract: A novel wind chime, whereby deficiencies in the prior art, for example, it is necessary to drill holes in the wind chime tubes and grind the holes, which consumes time and manpower, affects beauty of the wind chime, deteriorates tone quality thereof and is liable to cause safety hazards, are addressed, and the wind chime, including a connection ring, a plurality of suspension cords passing the connection ring, a hanger connected at upper ends of the plurality of suspension cords, a striker connected at lower ends of the plurality of suspension cord and a plurality of wind chime tubes, jump rings are connected respectively at the lower ends of the plurality of suspension cords, limiting and connection structures are respectively provided between central positions of the jump rings and the plurality of suspension cords, and the jump rings are connected at inner sides of the plurality of wind chime tubes.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: May 28, 2024
    Assignee: LIVE OAK (YIWU) CO., LTD.
    Inventor: Chih Chen Chiang
  • Integrated circuit structure, and method for forming thereof
    Patent number: 11996375
    Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a die that contains a substrate, an interconnection structure, active connectors and dummy connectors. The interconnection structure is disposed over the substrate. The active connectors and the dummy connectors are disposed over the interconnection structure. The active connectors are electrically connected to the interconnection structure, and the dummy connectors are electrically insulated from the interconnection structure.
    Type: Grant
    Filed: February 22, 2023
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chao Mao, Chin-Chuan Chang, Szu-Wei Lu, Kun-Tong Tsai, Hung-Chih Chen