Abstract: An integrated circuit (IC) structure includes a semiconductor substrate, a bottom electrode routing, a capacitor structure, a top electrode routing. The bottom electrode routing is over the semiconductor substrate. The capacitor structure is over the bottom electrode routing. The capacitor structure includes a bottom metal layer, a middle metal layer above the bottom metal layer, and a top metal layer above the middle metal layer. When viewed in a plan view, the top metal layer has opposite straight edges extending along a first direction and opposite square wave-shaped edges connecting the opposite straight edges, the square wave-shaped edges each comprise alternating first and second segments extending along a second direction perpendicular to the first direction, and third segments each connecting adjacent two of the first and second segments, wherein the third segments extend along the first direction.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a resistive element over the substrate. The semiconductor device structure also includes a thermal conductive element over the substrate. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line, and the first imaginary line and the second imaginary line intersect at a center of the main surface.

Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.

Abstract: A semiconductor structure, including a substrate, a first well, a second well, a first doped region, a second doped region, a first gate structure, a first insulating layer, and a first field plate structure. The first and second wells are disposed in the substrate. The first doped region is disposed in the first well. The second doped region is disposed in the second well. The first gate structure is disposed between the first and second doped regions. The first insulating layer covers a portion of the first well and a portion of the first gate structure. The first field plate structure is disposed on the first insulating layer, and it partially overlaps the first gate structure. Wherein the first field plate structure is segmented into a first partial field plate and a second partial field plate separated from each other along a first direction.

Abstract: A method for parking detection and identification of moveable apparatus, comprising following steps of: generating a magnetic field signal containing an unique identifier for identifying the moveable apparatus by a magnetic field generator disposed in the moveable apparatus; measuring magnetic field respectively by two magnetic field sensors of a magnetic field sensing apparatus disposed in a moveable-apparatus parking place or its peripheral area, wherein a first and a second magnetic field measurements are measured; and calculating a magnetic field measurement difference for obtaining the unique identifier, wherein the magnetic field measurement difference is a magnitude of a difference of the first and the second magnetic field measurements, or a magnitude of a difference of a first magnetic field component of the first magnetic field measurement along a characteristic direction and a second magnetic field component of the second magnetic field measurement along the characteristic direction.

Abstract: A semiconductor package includes a partitioned package substrate that is composed of multiple discrete substrates arranged in a side-by-side manner. The discrete substrates include a central substrate and peripheral substrates surrounding the central substrate. At least one integrated circuit die is mounted on a first surface of the partitioned package substrate. A plurality of solder balls is mounted on a second surface of the partitioned package substrate opposite to the first surface.

Abstract: A semiconductor package includes a partitioned package substrate composed of substrate parts arranged in a side-by-side manner; an integrated circuit die mounted on a first surface of the partitioned package substrate; and solder balls mounted on a second surface of the partitioned package substrate opposite to the first surface.

Abstract: A clock synthesizer is provided. A clock buffer is configured to store an input clock signal. A Duty Cycle Corrector (DCC) circuit is connected to the clock buffer. The DCC circuit is configured to receive the input clock signal from the clock buffer, receive a control signal, and adjust a duty cycle of the input clock signal based on the control signal. An output clock signal comprising the duty cycle corrected input clock signal is generated. The output clock signal is provided. A current source is configured to sink a clamping current to the DCC circuit.

Abstract: A multiband antenna comprises a dielectric substrate with a first surface defining an annular ledge and a central recess with a plurality of pockets. A MIMO radiator body is disposed in the central recess having a first surface defining a plurality of lobes which are disposed in respective ones of the plurality of pockets and having a second surface defining an outer rim and a central shelf A radiator ring is disposed at the annular ledge so that the radiator ring and the outer rim converge along an annular gap therebetween. A plurality of MIMO feed lines provide external connection to respective lobes. The MIMO radiator body and the radiator ring provide a substantially horizontally-directed radiation pattern (e.g., for terrestrial signals). At least one low-profile radiator on the central shelf provides a substantially circularly polarized or vertically-directed radiation pattern for receiving signals radiated from a satellite.

Abstract: A display panel and a spliced display are provided. The display panel includes a substrate, a plurality of light-emitting elements, a driving circuit, and an optical sensor. The substrate includes a through hole, and the through hole includes a hole. The plurality of the light-emitting elements are disposed on the substrate. The through hole is located in a region between two of the plurality of the light-emitting elements. The driving circuit is disposed on the substrate and electrically connected to the plurality of the light-emitting elements. The optical sensor is disposed corresponding to the through hole and receives sensing light through the hole. The width W of the hole meets the equation of H?W<D. H is the depth of the hole, and D is the distance between the two of the plurality of the light-emitting elements.

Abstract: A thermally insulating fixture includes a self-tapping screw, a fixed member mounted on the self-tapping screw, and a thermally insulating member wrapping the fixed member. The fixed member is provided with a first through hole. The thermally insulating member is provided with a second through hole and a positioning groove. The self-tapping screw extends through the second through hole of the thermally insulating member and the first through hole of the fixed member. A thermally insulating cover is mounted in the positioning groove and covers the self-tapping screw. The thermally insulating cover has a receiving space which receives the self-tapping screw. The thermally insulating cover has a positioning flange which is positioned in the positioning groove when the thermally insulating cover covers the head of the self-tapping screw.

Abstract: In some examples, an electronic device includes an image sensor to capture a source image. In some examples, the electronic device includes a processor to determine, in the source image, a first region that depicts a first person and a second region that depicts a second person. In some examples, the processor is to, in response to determining that the first person is further away than the second person relative to the image sensor based on the first region and the second region, generate a first focus cell that depicts the first person alone. In some examples, the processor is to generate a macro view of the source image that depicts the first person and the second person. In some examples, the processor is to instruct display of a compound image including the macro view and the first focus cell.

Abstract: Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.

Abstract: A semiconductor device includes a first integrated circuit die and a second integrated circuit die. The first integrated circuit die includes a conductive paste on a first surface of the first integrated circuit die, wherein the conductive paste is in direct contact with the first surface of the first integrated circuit die. The second integrated circuit die is disposed aside the first integrated circuit die, wherein a surface of the conductive paste is substantially coplanar with a surface of the second integrated circuit die.

Abstract: A method includes forming a first connector and a second connector over a first wafer and a second wafer, respectively, in which each of the first and second connectors are formed by forming an opening in a dielectric layer; depositing a first metal layer in the opening, in which the first metal layer has a nano-twinned structure with (111) orientation; and depositing a second metal layer over the first metal layer, the second metal layer and the first metal layer being made of different materials, in which the second metal layer has a nano-twinned structure with (111) orientation; attaching the first wafer to the second wafer, such that that the second metal layer of the first connector on the first wafer is in contact with the second metal layer of the second connector on the second wafer; and performing a thermo-compression process to bond the first and second wafers.

Abstract: An integrated circuit (IC) structure includes a semiconductor substrate, a bottom electrode routing, a capacitor structure, a top electrode routing. The bottom electrode routing is over the semiconductor substrate. The capacitor structure is over the bottom electrode routing. The capacitor structure includes a bottom metal layer, a middle metal layer above the bottom metal layer, and a top metal layer above the middle metal layer. When viewed in a plan view, the top metal layer has opposite straight edges extending along a first direction and opposite square wave-shaped edges connecting the opposite straight edges, the square wave-shaped edges each comprise alternating first and second segments extending along a second direction perpendicular to the first direction, and third segments each connecting adjacent two of the first and second segments, wherein the third segments extend along the first direction.

Abstract: An interface for a semiconductor chip provided herein includes bonds. The interface has device layout channels and via layout channels and including a circuitry and routing structure. Each device layout channel is located between two via layout channels in a first direction to form a unit layout channel extending in a second direction intersecting the first direction. The bonds are arranged in a bond map following the via layout channels and outside the device layout channels. Most adjacent two of the bonds in the second direction are arranged in a vertical pitch, two bonds at two opposite sides of the device layout channel in the first direction are arranged in a transversal pitch, and the transversal pitch is greater than the vertical pitch. A portion of the circuitry and routing structure is disposed in the device layout channels. A semiconductor device including stacked semiconductor chips is also provided.

Abstract: In some examples, an electronic device includes an image sensor to capture a source image. In some examples, the electronic device includes a processor to determine, in the source image, a first region that depicts a first person and a second region that depicts a second person. In some examples, the processor is to, in response to determining that the first person is further away than the second person relative to the image sensor based on the first region and the second region, generate a first focus cell that depicts the first person alone. In some examples, the processor is to generate a macro view of the source image that depicts the first person and the second person. In some examples, the processor is to instruct display of a compound image including the macro view and the first focus cell.

Abstract: In some implementations, the disclosed systems and methods can include one or more tinting elements (e.g., flip-down blacked-out lenses, a blacked-out slider, or a blacked-out removeable cover) configured to cover the lenses of the MR glasses. In some implementations, the disclosed systems and methods can be coupled to one or more micro electrical motors configured to drive the clear fluid into and out of the pairs of clear flexible membranes, in order to make the focus tunable lenses concave to correct myopia, or convex to correct hyperopia or presbyopia. In some implementations, the disclosed systems and methods can be directed to online calibration of headset proximity sensors to mitigate after factory sensor drift and prevent automatic OFF and ON system failures.

Abstract: A wearable device and a method for performing a registration process in the wearable device are provided. The wearable device includes a light source, a light sensor and a microcontroller that performs the method. In the method, the light source is activated to emit a detection light and the light sensor senses a reflected light. A light intensity of the reflected light is calculated. A registration value is produced based on the light intensity. Specifically, the detection light with a specific frequency to be registered in the registration value is used as a reference to detect whether the wearable device is properly worn by a person. For example, since the wearable device can be worn on the person's wrist, the registration value is used to detect whether the wearable device is away from the wrist.