Abstract: A method includes forming a first connector and a second connector over a first wafer and a second wafer, respectively, in which each of the first and second connectors are formed by forming an opening in a dielectric layer; depositing a first metal layer in the opening, in which the first metal layer has a nano-twinned structure with (111) orientation; and depositing a second metal layer over the first metal layer, the second metal layer and the first metal layer being made of different materials, in which the second metal layer has a nano-twinned structure with (111) orientation; attaching the first wafer to the second wafer, such that that the second metal layer of the first connector on the first wafer is in contact with the second metal layer of the second connector on the second wafer; and performing a thermo-compression process to bond the first and second wafers.

Abstract: An integrated circuit (IC) structure includes a semiconductor substrate, a bottom electrode routing, a capacitor structure, a top electrode routing. The bottom electrode routing is over the semiconductor substrate. The capacitor structure is over the bottom electrode routing. The capacitor structure includes a bottom metal layer, a middle metal layer above the bottom metal layer, and a top metal layer above the middle metal layer. When viewed in a plan view, the top metal layer has opposite straight edges extending along a first direction and opposite square wave-shaped edges connecting the opposite straight edges, the square wave-shaped edges each comprise alternating first and second segments extending along a second direction perpendicular to the first direction, and third segments each connecting adjacent two of the first and second segments, wherein the third segments extend along the first direction.

Abstract: An interface for a semiconductor chip provided herein includes bonds. The interface has device layout channels and via layout channels and including a circuitry and routing structure. Each device layout channel is located between two via layout channels in a first direction to form a unit layout channel extending in a second direction intersecting the first direction. The bonds are arranged in a bond map following the via layout channels and outside the device layout channels. Most adjacent two of the bonds in the second direction are arranged in a vertical pitch, two bonds at two opposite sides of the device layout channel in the first direction are arranged in a transversal pitch, and the transversal pitch is greater than the vertical pitch. A portion of the circuitry and routing structure is disposed in the device layout channels. A semiconductor device including stacked semiconductor chips is also provided.

Abstract: In some examples, an electronic device includes an image sensor to capture a source image. In some examples, the electronic device includes a processor to determine, in the source image, a first region that depicts a first person and a second region that depicts a second person. In some examples, the processor is to, in response to determining that the first person is further away than the second person relative to the image sensor based on the first region and the second region, generate a first focus cell that depicts the first person alone. In some examples, the processor is to generate a macro view of the source image that depicts the first person and the second person. In some examples, the processor is to instruct display of a compound image including the macro view and the first focus cell.

Abstract: In some implementations, the disclosed systems and methods can include one or more tinting elements (e.g., flip-down blacked-out lenses, a blacked-out slider, or a blacked-out removeable cover) configured to cover the lenses of the MR glasses. In some implementations, the disclosed systems and methods can be coupled to one or more micro electrical motors configured to drive the clear fluid into and out of the pairs of clear flexible membranes, in order to make the focus tunable lenses concave to correct myopia, or convex to correct hyperopia or presbyopia. In some implementations, the disclosed systems and methods can be directed to online calibration of headset proximity sensors to mitigate after factory sensor drift and prevent automatic OFF and ON system failures.

Abstract: A wearable device and a method for performing a registration process in the wearable device are provided. The wearable device includes a light source, a light sensor and a microcontroller that performs the method. In the method, the light source is activated to emit a detection light and the light sensor senses a reflected light. A light intensity of the reflected light is calculated. A registration value is produced based on the light intensity. Specifically, the detection light with a specific frequency to be registered in the registration value is used as a reference to detect whether the wearable device is properly worn by a person. For example, since the wearable device can be worn on the person's wrist, the registration value is used to detect whether the wearable device is away from the wrist.

Abstract: A package structure includes a semiconductor die and a first redistribution circuit structure. The first redistribution circuit structure is disposed on and electrically connected to the semiconductor die, and includes a first build-up layer. The first build-up layer includes a first metallization layer and a first dielectric layer laterally wrapping the first metallization layer, wherein at least a portion of the first metallization layer is protruded out of the first dielectric layer.

Abstract: An example non-transitory machine-readable storage medium includes instructions to, when executed by the processor, identify an object depicted in a video scene, wherein the video scene is displayed in a graphical user interface (GUI). The example instructions are executable to 1) identify coordinates of the object depicted in the video scene, wherein the coordinates are relative to the GUI and 2) identify coordinates of an inset window which is smaller than the GUI and overlaps the video scene. The example instructions are executable to compare the coordinates of the object with the coordinates of the inset window to determine an overlap of the inset window with the object. Responsive to an identified overlap of the inset window and the object, the instructions are executable to alter a display characteristic of the inset window to avoid the overlap of the inset window with the object.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes first and second gate structures formed over a semiconductor substrate and a multilayer gate isolation structure separating the first gate structure from the second gate structure. The multilayer gate isolation structure includes a first insulating feature adjacent to upper portions of the first gate structure and the second gate structure, and a second insulating feature separating the semiconductor substrate from the first insulating feature. The material of the second insulating feature is different than that of the first insulating feature. The second insulating feature has a lower dielectric constant or lower etch resistance than the first insulating feature.

Abstract: A retaining ring can be shaped by machining or lapping the bottom surface of the ring to form a shaped profile in the bottom surface. The bottom surface of the retaining ring can include flat, sloped and curved portions. The lapping can be performed using a machine that dedicated for use in lapping the bottom surface of retaining rings. During the lapping the ring can be permitted to rotate freely about an axis of the ring. The bottom surface of the retaining ring can have curved or flat portions.

Abstract: A method of operating a transport system includes detecting an anomalous condition of a wafer transfer vehicle; sending the wafer transfer vehicle along a rail to a diagnosis station adjacent to the rail; and inspecting properties of the wafer transfer vehicle, such as a speed, a weight, an audio frequency, a noise level, a temperature, and an image of the wafer transfer vehicle, by using the diagnosis station.

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate. The photoresist layer includes a photoresist composition includes a polymer. The polymer includes a monomer unit having a pendant sensitizer and crosslinking group, and a monomer unit having a pendant acid labile group. The photoresist layer is selectively exposed to actinic radiation, and the selectively exposed photoresist layer is developed.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack over a substrate. The first gate stack includes a first gate electrode and a dielectric layer between the first gate electrode and the substrate, and the first gate electrode has a void. The method includes oxidizing a side portion of the first gate electrode to form an oxide layer over the first gate electrode. The oxide layer fills the void.

Abstract: An electronic device is provided and includes a first voltage trace, a second voltage trace, a first region electrode, a second region electrode, and a voltage source module. The second voltage trace is electrically insulated from the first voltage trace, the first region electrode is electrically connected to the first voltage trace, and the second region electrode is electrically connected to the second voltage trace. The voltage source module provides a first driving voltage to the first voltage trace and provides a second driving voltage to the second voltage trace, in which the first driving voltage is different from the second driving voltage. In a top-view direction of the electronic device, the first voltage trace is separated from the second voltage trace, and the first voltage trace and the second voltage trace are formed of a conductive layer.

Abstract: The present invention discloses an electromagnetic air pump including an air chamber operable to be compressed or expanded. The air chamber is defined by a platform surface and a rubber cap operable to be pressed downward. The rubber cap includes a support and a cover. During the operation of the electromagnetic air pump, the cover is configured to bear against the support with the platform surface when the cover is pressed downward. When the air chamber is compressed or expanded, each pair of geometrically symmetrical parts of the cover corresponds to a pair of displacement changes relative to the platform surface, wherein a difference between the pair of displacement changes is not greater than 5%. Thus, the rubber cap is provided with an effect of a substantially uniform stress.

Abstract: A semiconductor device includes a first electrode layer, a ferroelectric layer, and a second electrode layer. A material of the ferroelectric layer comprises a ferroelectric material doped with a first dopant and a second dopant different from the first dopant, and the first dopant comprises cerium. The ferroelectric layer is disposed between the first electrode layer and the second electrode layer.

Abstract: A down-converted voltage regulator is provided. The first energy storage element provides a pre-charged voltage between a connection terminal and a ground terminal during the first phase. The second energy storage element has a first terminal, and it has a second terminal coupled to the output terminal of the voltage regulator. The third energy storage element is coupled between the output terminal of the voltage regulator and the ground terminal. During the first phase, the first terminal of the second energy storage element is coupled to the first energy storage element through the connection terminal to receive the pre-charged voltage. During the second phase, the first energy storage element is coupled between the input terminal and the output terminal of the voltage regulator to be pre-charged to store the pre-charged voltage, and the first terminal of the second energy storage element is coupled to the ground terminal.

Abstract: A dual-input power switching system includes a first DC power source, a second DC power source, a DC conversion circuit, and a boost-up circuit. The first DC power source provides a first DC voltage, and the second DC power source provides a second DC voltage. The DC conversion circuit receives the first DC voltage or the second DC voltage being an input voltage, and converts the input voltage to supply power to a load. The boost-up circuit provides a hold-up voltage to boost up the input voltage when the first DC power source stops supplying power to lead to power drop of the input voltage, such that the input voltage reaches to a specific voltage that is greater than the second DC voltage and afterward naturally decreases to be less than or equal to the second DC voltage.

Abstract: A multilayer structure for lithography patterning is provided. The multilayer structure includes a substrate, a bottom anti-reflective coating (BARC) layer over the substrate, and a photoresist layer over the BARC layer. The BARC layer includes a polymer and a hydrolysis promoting agent. The photoresist layer includes an organometallic dimer obtained by partial hydrolysis of a precursor organometallic compound comprising hydrolysable ligands.