Patents by Inventor Chih Chen

Chih Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250047201
    Abstract: A power converter is coupled between a power source and multiple loads, and the power converter includes a first switch module. The switch module includes an inductor, a first switch, a second switch, a third switch, and a fourth switch. The first switch, the second switch, the third switch, and the fourth switch are configured to be turned on or turned off so that the inductor is stored energy or released energy to converter the power source into multiple voltages to the multiple loads.
    Type: Application
    Filed: September 20, 2023
    Publication date: February 6, 2025
    Inventors: Hung-Chieh LIN, Yi-Ping HSIEH, Hsin-Chih CHEN, Hung-Yu HUANG
  • Patent number: 12218009
    Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a front side of a wafer, the wafer having a plurality of dies at the front side of the wafer, the first dielectric layer having a first shrinkage ratio smaller than a first pre-determined threshold; curing the first dielectric layer at a first temperature, where after curing the first dielectric layer, a first distance between a highest point of an upper surface of the first dielectric layer and a lowest point of the upper surface of the first dielectric layer is smaller than a second pre-determined threshold; thinning the wafer from a backside of the wafer; and performing a dicing process to separate the plurality of dies into individual dies.
    Type: Grant
    Filed: August 1, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Che Tu, Wei-Chih Chen, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo, Chen-Hua Yu
  • Patent number: 12218239
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy, gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Grant
    Filed: May 24, 2023
    Date of Patent: February 4, 2025
    Assignee: Mosaid Technologies Incorporated
    Inventors: Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
  • Patent number: 12218412
    Abstract: An antenna structure capable of transmitting a WiGig band for a head-mounted wireless transmission display device including a display screen and an overhead device is disclosed. The antenna structure includes at least two body portions, each of the body portions having at least a signal transceiving end, the body portions are respectively arranged at left and right sides of the display screen, and signal transceiving ends of the body portions are extended outward from the left and right sides of the display screen respectively.
    Type: Grant
    Filed: January 31, 2024
    Date of Patent: February 4, 2025
    Assignee: HTC Corporation
    Inventors: Sheng Cherng Lin, Hsiao-Ling Chan, Chen-Hao Chang, Chien-Chih Chen
  • Patent number: 12219843
    Abstract: An electronic device includes a conductive wire having a metal portion with openings. The openings include a first opening and a second opening arranged along a first direction, and the metal portion includes the first to fourth extending portions and the first to fourth joint portions. The first opening is surrounded by the first extending portion, the second extending portion, the first joint portion, and the second joint portion. The second opening is surrounded by the third extending portion, the fourth extending portion, the third joint portion, and the fourth joint portion. Along the first direction, a ratio of a first width sum of widths of the first extending portion, the second extending portion, the third extending portion, and the fourth extending portion to a second width sum of widths of the first joint portion and the third joint portion is in a range from 0.8 to 1.2.
    Type: Grant
    Filed: March 18, 2024
    Date of Patent: February 4, 2025
    Assignee: InnoLux Corporation
    Inventors: Ya-Wen Lin, Chien-Chih Chen, Yen-Hsi Tu, Cheng-Wei Chang, Shu-Hui Yang
  • Publication number: 20250038148
    Abstract: A method includes forming a metal post over a first redistribution structure; attaching a first device die to the first redistribution structure, the first device die comprising a through via embedded in a semiconductor substrate; encapsulating the metal post and the first device die in an encapsulant, a first top surface of the encapsulant being level with a second top surface of the semiconductor substrate; recessing the second top surface to expose the through via; forming a dielectric isolation layer around the through via; forming a dielectric layer over the dielectric isolation layer; etching the dielectric layer to form a first opening and a second opening in the dielectric layer; forming a first metal via in the first opening and a second metal via in the second opening; and forming a second redistribution structure over the dielectric layer.
    Type: Application
    Filed: January 3, 2024
    Publication date: January 30, 2025
    Inventors: Wei-Chih Chen, Jhih-Yu Wang, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20250038439
    Abstract: An electrical card connector is disclosed in this application, including an insulating base, a plurality of first conductive terminals, a plurality of second conductive terminals and a pair of balance terminals. The pair of balance terminals are fixed on two opposite side walls. Elastic pressure arms of the pair of balance terminals commonly clamp two side edges of an electronic card when the electronic card is inserted into an accommodation space and touches first elastic arms of the first conductive terminals. Sliding portions of the pair of balance terminal slide along the corresponding side walls when the elastic pressure arms clamp the electronic card and the electronic card continues to be inserted. The sliding portions enter openings of the corresponding side walls to release at least a portion of a clamping force when the electronic card touches second elastic arms of the second conductive terminals.
    Type: Application
    Filed: January 10, 2024
    Publication date: January 30, 2025
    Inventor: Hsin Chih CHEN
  • Publication number: 20250040100
    Abstract: A liquid cooling rack assembly for a computing system includes a first cabinet rack configured to receive within a plurality of computing devices with heat-generating electronic components; and a second cabinet rack configured to receive coolant components. The second cabinet rack has a plurality of movable trays, each tray of the plurality of movable trays being movable generally horizontally and independently of other trays of the plurality of movable trays. The liquid cooling rack assembly further includes a plurality of cooling pumps. Each pump of the plurality of cooling pumps is placed on a respective one of the plurality of movable trays, and each pump is independently serviceable from other pumps of the plurality of cooling pumps based on independent movement of a respective tray.
    Type: Application
    Filed: September 5, 2023
    Publication date: January 30, 2025
    Inventors: Chao-Jung CHEN, Ta-Chih CHEN, Chih-Ming CHEN
  • Patent number: 12204806
    Abstract: A display control chip includes a first memory and a computing circuit. The first memory is configured to store a plurality of character images respectively corresponds to a plurality of characters of a character encoding format. The computing circuit is coupled with the first memory, and is configured to receive first update data generated by encoding input data according to the character encoding format, and is configured to use the first update data to update text data in a second memory. When the computing circuit reads the text data in the second memory, the computing circuit is configured to: search among the plurality of character images to find a plurality of target images corresponding to the text data; and output first display data according to the plurality of target images, in which the first display data is for generating a first display picture including the plurality of target images.
    Type: Grant
    Filed: August 11, 2023
    Date of Patent: January 21, 2025
    Assignee: Realtek Semiconductor Corporation
    Inventors: Yung-Chih Chen, Wei-Chih Lin, Jui-Te Wei, Po-An Chen
  • Patent number: 12204364
    Abstract: Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: January 21, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Wei Chih Chen
  • Patent number: 12196496
    Abstract: A liquid-cooled cooling structure includes a cooling main body having a condensation chamber and an evaporation chamber arranged vertically therein; a separation member arranged between and separating the condensation chamber and the evaporation chamber, and having a first through hole and a second through hole communicating with the condensation chamber and the evaporation chamber, a dimension of the first through hole being greater than that of the second through hole; a longitudinal partition board received in the condensation chamber and arranged between the first through hole and the second through hole and separating the condensation chamber into a first channel and a second channel; cooling fins extended from an outer perimeter of the cooling main body.
    Type: Grant
    Filed: September 25, 2022
    Date of Patent: January 14, 2025
    Assignee: AIC INC.
    Inventors: Yen-Chih Chen, Chi-Fu Chen, Wei-Ta Chen, Hung-Hui Chang
  • Publication number: 20250013119
    Abstract: An image displacement device includes a first grating and a second grating. The first grating has a first surface and a second surface opposite the first surface, the first surface receives image beams, and the image beams leave the first grating by the second surface. The second grating is disposed downstream from the first grating in a light path and has a third surface and a fourth surface opposite the third surface. The third surface receives the image beams, and the image beams leave the second grating by the fourth surface. The image beams are projected to form a plane image comprised of pixels, each pixel is displaced in a direction by the image displacement device, and a displacement of each pixel is smaller than five times a width of one pixel.
    Type: Application
    Filed: September 19, 2024
    Publication date: January 9, 2025
    Inventors: Ming-Chih CHEN, YA-LING HSU
  • Publication number: 20250015041
    Abstract: A method includes forming a first conductive feature over a first semiconductor structure; forming a first dielectric layer over the first conductive feature and the first semiconductor structure; removing a portion of the first dielectric layer to expose a top surface of the first conductive feature; forming a second conductive feature over a second semiconductor structure, wherein the first and second conductive features comprise nanotwinned copper; forming a second dielectric layer over the second conductive feature and the second semiconductor structure, wherein the second dielectric layer comprises a same material as the first dielectric layer; removing a portion of the second dielectric layer to expose a top surface of the second conductive feature; and performing a hybrid bonding process to bond the first dielectric layer to the second dielectric layer and bond the first conductive feature to the second conductive feature.
    Type: Application
    Filed: July 6, 2023
    Publication date: January 9, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Chih CHEN, Pin-Syuan HE, Kai-Cheng SHIE
  • Patent number: 12191222
    Abstract: A redistribution structure is made using filler-free insulating materials with a high shrinkage rate. As a result, good planarity may be achieved without the need to perform a planarization of each insulating layer of the redistribution structure, thereby simplifying the formation of the redistribution structure.
    Type: Grant
    Filed: June 15, 2023
    Date of Patent: January 7, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chih Chen, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20250005842
    Abstract: A technique for performing ray tracing operations is provided. The technique includes traversing a bounding volume hierarchy for a ray to arrive at a bounding box without use of a neural network; perform a feature vector lookup using modified polar coordinates characterizing the ray relative to the bounding box to obtain a set of feature vectors; and obtaining output with the neural network using the set of feature vectors.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Shin Fujieda, Takahiro Harada, Chih-Chen Kao
  • Publication number: 20250007389
    Abstract: A circulating current suppression method of a power system having a plurality of power modules is provided. Each power module includes a high-voltage bus, a low-voltage bus and a balance circuit having a neutral voltage. The circulating current suppression method includes: in each balance circuit, disposing a first capacitor electrically coupled between the high-voltage bus and the neutral voltage, and disposing a second capacitor electrically coupled between the neutral voltage and the low-voltage bus; acquiring a current effective value of an input of each power module; if detecting that the current effective value of at least one power module doesn't remain at a current reference value, determining that a circulating current occurs in the at least one power module; and operating the balance circuit of the at least one power module to charge the first capacitor or the second capacitor to regulate the neutral voltage for suppressing the circulating current.
    Type: Application
    Filed: September 7, 2023
    Publication date: January 2, 2025
    Inventors: Hsin-Chih Chen, Li-Hung Wang, Chao-Li Kao, Yi-Ping Hsieh, Hung-Chieh Lin
  • Patent number: 12180576
    Abstract: A physical vapor deposition (PVD) target for performing a PVD process is provided. The PVD target includes a backing plate and a target plate coupled to the backing plate. The target plate includes a sputtering source material and a dopant, with the proviso that the dopant is not impurities in the sputtering source material. The sputtering source material includes a diffusion barrier material.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: December 31, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hsi Wang, Yen-Yu Chen, Yi-Chih Chen, Shih-Wei Bih
  • Patent number: 12181786
    Abstract: A wavelength conversion element includes a rotatable disc, a first spoiler structure and a second spoiler structure. The rotatable disc has a supporting surface and a back surface opposite to the supporting surface. The first spoiler structure is disposed on the supporting surface and arranged along a first track surrounding a center of the rotatable disc. The second spoiler structure is disposed on the back surface and arranged along a second track surrounding the center. A centroid of at least one of the first spoiler structure and the second spoiler structure is deviated from the center. A projection device adopting the aforementioned wavelength conversion element is also provided. The wavelength conversion element of the invention can reduce the initial unbalance and the projection device of the invention can improve the durability.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: December 31, 2024
    Assignee: Coretronic Corporation
    Inventor: Fa-Chih Chen
  • Publication number: 20240426532
    Abstract: A refrigerant system including a compressor, an oil separator, an oil solenoid valve, a condenser, an evaporator, a bypass pipe, and a bypass solenoid valve is disclosed. The oil separator is connected to an output end of the compressor. The oil solenoid valve is disposed between the oil cooler and the compressor. The condenser is connected to the oil separator. The evaporator is connected to the condenser. The bypass pipe has a first end and a second end opposite to the first end. The first end is connected between the oil separator and the condenser, and the second end is connected between the evaporator and an input end of the compressor. The bypass solenoid valve is disposed on the bypass pipe. A controlling method for the refrigerant system is also disclosed.
    Type: Application
    Filed: May 13, 2024
    Publication date: December 26, 2024
    Applicant: Fu Sheng Industrial Co. Ltd.
    Inventors: Wei-Hsu Lin, Yao-Chung Yu, Xuan-Fu Li, Yu-Chih Chen
  • Publication number: 20240421277
    Abstract: A pixel structure includes a first light-emitting diode for emitting a first light, wherein the first light-emitting diode has a first semiconductor layer, a first light-emitting surface, and a first electrode under the first semiconductor layer away from the first light-emitting surface; a second light-emitting diode for emitting a second light, wherein the second light-emitting diode has a second semiconductor layer, a second light-emitting surface, and a second electrode under the second semiconductor layer away from the second light-emitting surface; a dielectric layer surrounding and contacting the first semiconductor layer and the second light-emitting diode and exposing the first light-emitting surface, the first electrode, the second light-emitting surface and the second electrode; a common conductive structure having a semiconductor layer and a metal layer; and a light-transmitting conductive layer covering and electrical connecting the first light-emitting diode, the second light-emitting diode and
    Type: Application
    Filed: June 13, 2024
    Publication date: December 19, 2024
    Inventors: Min-Hsun HSIEH, Ying-Yang SU, Chien-Chih CHEN, Wei-Shan HU, Ching-Tai CHENG, Chung-Che TENG, Tai-Ni CHU, Hsin-Mao LIU