Abstract: A shunting device used to transport workpieces comprises a plurality of rotating shafts parallel to one another and arranged in arrays, a plurality of first omnidirectional wheels, and a plurality of second omnidirectional wheels. The first omnidirectional wheels and the second omnidirectional wheels are each wrapped around a corresponding one of the rotating shafts in a matrix. The first omnidirectional wheels and the second omnidirectional wheels are alternatively arranged along the corresponding one of the plurality of rotating shafts and a second direction perpendicular to the plurality of rotating shafts. A plurality of first driven rollers of the first omnidirectional wheels and a plurality of second driven rollers of the second omnidirectional wheels are mirror-symmetrical along at least one of a third direction parallel to the plurality of rotating shafts and the second direction.

Abstract: A single bridge magnetic field sensor includes a fluxguide mounted to a surface of a substrate. A bridge unit includes first, second, third, and fourth magnetoresistive elements mounted around the fluxguide and mounted on the surface of the substrate. A switching circuit is electrically connected to two voltage inputs, two grounding terminals, two voltage output terminals, and the four magnetoresistive elements. The switching circuit can proceed with circuit switching according to a magnetic field in each axis direction to be measured, thereby changing electrical connection between the voltage inputs, the grounding terminals, the voltage output terminals, and the four magnetoresistive elements. A measuring unit is electrically connected to the two voltage output terminals and the four magnetoresistive elements.

Abstract: A single bridge magnetic field sensor includes a fluxguide mounted to a surface of a substrate. A bridge unit includes first, second, third, and fourth magnetoresistive elements mounted around the fluxguide and mounted on the surface of the substrate. A switching circuit is electrically connected to two voltage inputs, two grounding terminals, two voltage output terminals, and the four magnetoresistive elements. The switching circuit can proceed with circuit switching according to a magnetic field in each axis direction to be measured, thereby changing electrical connection between the voltage inputs, the grounding terminals, the voltage output terminals, and the four magnetoresistive elements. A measuring unit is electrically connected to the two voltage output terminals and the four magnetoresistive elements.

Abstract: The reliability of an integrated circuit is inferred from the operational characteristics of sample metal oxide semiconductor (MOS) devices switchably coupled to drain/source bias and gate input voltages that are nominal, versus voltage and current conditions that elevate stress and cause temporary or permanent degradation, e.g., hot carrier injection (HCI), bias temperature instability (BTI, NBTI, PBTI), time dependent dielectric breakdown (TDDB). The MOS devices under test (preferably both PMOS and NMOS devices tested concurrently or in turn) are configured as current sources in the supply of power to a ring oscillator having cascaded inverter stages, thereby varying the oscillator frequency as a measure of the effects of stress on the devices under test, but without elevating the stress applied to the inverter stages.

Abstract: A solar cell includes a substrate, a first lightly-doped region, a second lightly-doped region, a second heavily-doped region, a first electrode and a second electrode. The first lightly-doped region having a first doping type is disposed in a first surface of the substrate. The second lightly-doped region and the second heavily-doped region having a second doping type different from the first doping type are disposed in a second surface of the substrate. The first electrode is disposed on the first surface of the substrate, and the second electrode is disposed on the second surface of the substrate.

Abstract: A pipelined ADC includes a first, second, and third pairs of comparators. The first pair of comparators compare an input voltage to a first positive reference voltage and to a first negative reference voltage. The second pair of comparators compare the input voltage to a second positive reference voltage and to a second negative reference voltage. Each comparator of the first and second pairs of comparators outputs a digital signal to an encoder. A third pair of comparators compares the input voltage to a third positive reference voltage and to a third negative reference voltage, and a comparator compares the input voltage to ground. The comparator and each comparator of the third pair of comparators is configured to output respective digital signals to an encoder. A multiplying digital-to-analog converter outputs a voltage based on the input voltage, an output from the encoder, and an output of the random number generator.

Abstract: A pipelined ADC includes a first, second, and third pairs of comparators. The first pair of comparators compare an input voltage to a first positive reference voltage and to a first negative reference voltage. The second pair of comparators compare the input voltage to a second positive reference voltage and to a second negative reference voltage. Each comparator of the first and second pairs of comparators outputs a digital signal to an encoder. A third pair of comparators compares the input voltage to a third positive reference voltage and to a third negative reference voltage, and a comparator compares the input voltage to ground. The comparator and each comparator of the third pair of comparators is configured to output respective digital signals to an encoder. A multiplying digital-to-analog converter outputs a voltage based on the input voltage, an output from the encoder, and an output of the random number generator.

Abstract: The reliability of an integrated circuit is inferred from the operational characteristics of sample metal oxide semiconductor (MOS) devices switchably coupled to drain/source bias and gate input voltages that are nominal, versus voltage and current conditions that elevate stress and cause temporary or permanent degradation, e.g., hot carrier injection (HCI), bias temperature instability (BTI, NBTI, PBTI), time dependent dielectric breakdown (TDDB). The MOS devices under test (preferably both PMOS and NMOS devices tested concurrently or in turn) are configured as current sources in the supply of power to a ring oscillator having cascaded inverter stages, thereby varying the oscillator frequency as a measure of the effects of stress on the devices under test, but without elevating the stress applied to the inverter stages.

Abstract: A nonvolatile analog memory has a floating gate point. The nonvolatile analog memory includes a capacitor, a first current source, a second current source and a current adjuster. The first current source controlled by a voltage value at the floating gate point and generates a first current. The second current source controlled by the voltage value at the floating gate point and generates a second current. The current adjuster receives the output voltage and a reference voltage and adjusts the first current and the second current based on the output voltage and the reference voltage. The current adjuster charges or discharges the capacitor to equalize the output voltage to the reference voltage.

Abstract: A nonvolatile analog memory has a floating gate point. The nonvolatile analog memory includes a capacitor. a first current source, a second current source and a current adjuster. The first current source controlled by a voltage value at the floating gate point and generates a first current. The second current source controlled by the voltage value at the floating gate point and generates a second current. The current adjuster receives the output voltage and a reference voltage and adjusts the first current and the second current based on the output voltage and the reference voltage. The current adjuster charges or discharges the capacitor to equalize the output voltage to the reference voltage.

Abstract: A nonvolatile analog memory has a floating gate point. The nonvolatile analog memory includes a first current source, a second current source, and a current adjuster. The first current source generates a first current, and the second current source generates a second current. The current adjuster turns on or turns off a current path of the second current according to a reference current and the first current. Furthermore, when the current path of the second current is turned on, the first current is adjusted according to the second current, such that the first current is equal to the reference current.

Abstract: A nonvolatile analog memory has a floating gate point. The nonvolatile analog memory includes a first current source, a second current source, and a current adjuster. The first current source generates a first current, and the second current source generates a second current. The current adjuster turns on or turns off a current path of the second current according to a reference current and the first current. Furthermore, when the current path of the second current is turned on, the first current is adjusted according to the second current, such that the first current is equal to the reference current.

Abstract: In a method of monitoring human physiological parameters and safe condition universally, the method is applied to a monitoring apparatus worn at an examinee's body and includes the steps of: monitoring the examinee's current plurality of physiological parameters and plurality of movement information; analyzing the movement information to determine whether or not the examinee is in motion; analyzing the physiological parameters to determine whether or not each physiological parameter is in compliance with a normal physiological standard preinstalled in the monitoring apparatus if the examinee is determined not in motion, and also determining whether or not each physiological parameter is in compliance with a normal physiological standard preinstalled in the monitoring apparatus; and issuing a first precaution reporting signal to an identified recipient and sending out the first precaution reporting signal via a wireless transmission, if the physiological parameters are incompliance with the normal physiologica

Abstract: Semiconductor substrate is disclosed having quantum wells having first bandgap, and quantum wells having second bandgap greater than first bandgap. Semiconductor structure is disclosed comprising substrate having quantum wells having given bandgap, other quantum wells modified to bandgap greater than given bandgap. Semiconductor substrate is disclosed comprising wafer having quantum wells, section of first bandgap, and section of second bandgap greater than first bandgap. Method for forming semiconductor substrate is provided, comprising providing wafer having given bandgap, depositing dielectric cap on portion and rapid thermal annealing to tuned bandgap greater than given bandgap. Semiconductor structure is disclosed comprising substrate having quantum wells modified by depositing cap and rapid thermal annealing to tuned bandgap greater than given bandgap.

Abstract: Semiconductor substrate is disclosed having quantum wells having first bandgap, and quantum wells having second bandgap less than second bandgap. Semiconductor structure is disclosed comprising substrate having quantum wells having given bandgap, other quantum wells modified to bandgap greater than given bandgap. Semiconductor substrate is disclosed comprising wafer having quantum wells, section of first bandgap, and section of second bandgap greater than first bandgap. Method for forming semiconductor substrate is provided, comprising providing wafer having given bandgap, depositing dielectric cap on portion and rapid thermal annealing to tuned bandgap greater than given bandgap. Semiconductor structure is disclosed comprising substrate having quantum wells modified by depositing cap and rapid thermal annealing to tuned bandgap greater than given bandgap.

Abstract: A sensor device that detects Laplacian electroencephalogram (LEEG) signals includes a signal acquisition module placed on a scalp of a subject to acquire brain signals. A signal processor is coupled or connected to the signal acquisition module to perform a Laplacian operation on the signals acquired by the signal acquisition module such that the noise signal is reduced to yield an analog LEEG signal with a high signal-to-noise (S/N) ratio.

Abstract: A shallow trench isolation (STI) structure and method of forming the same with reduced stress to improve charge mobility the method including providing a semiconductor substrate comprising at least one patterned hardmask layer overlying the semiconductor substrate; dry etching a trench in the semiconductor substrate according to the at least one patterned hardmask layer; forming one or more liner layers to line the trench selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride; forming one or more layers of trench filling material comprising silicon dioxide to backfill the trench; carrying out at least one thermal annealing step to relax accumulated stress in the trench filling material; carrying out at least one of a CMP and dry etch process to remove excess trench filling material above the trench level; and, removing the at least one patterned hardmask layer.

Abstract: A method of reducing oxide thickness variations in a STI pattern that includes both a dense trench array and a wide trench is described. A first HDP CVD step with a deposition/sputter (D/S) ratio of 9.5 is used to deposit a dielectric layer with a thickness that is 120 to 130% of the shallow trench depth. An etch back is performed in the same CVD chamber with NF3, SiF4 or NF3 and SiF4 to remove about 40 to 50% of the initial dielectric layer. A second HDP CVD step with a D/S ratio of 16 deposits an additional thickness of dielectric layer to a level that is slightly higher than after the first deposition. The etch back and second deposition form a smoother dielectric layer surface which enables a subsequent planarization step to provide filled STI features with a minimal amount of dishing in wide trenches.

Abstract: The method of presenting concurrent information about the electrical and mechanical activity of the heart using non-invasively obtained electrical and mechanical cardiac activity data from the chest or thorax of a patient comprises the steps of: placing at least three active Laplacian ECG sensors at locations on the chest or thorax of the patient; where each sensor has at least one outer ring element and an inner solid circle element, placing at least one ultrasonic sensor on the thorax where there is no underlying bone structure, only tissue, and utilizing available ultrasound technology to produce two or three-dimensional displays of the moving surface of the heart and making direct measurements of the exact sites of the sensors on the chest surface to determine the position and distance from the center of each sensor to the heart along a line orthogonal to the plane of the sensor and create a virtual heart surface; updating the measurements at a rate to show the movement of the heart's surface; monitoring

Abstract: A test region layout for testing shallow trench isolation gap fill characteristics is disclosed. Each test region further comprises at least one test pattern disposed in an interior portion of the test region. In a preferred embodiment, the test pattern is a square shape or, more preferably, two diametrically opposed “L” shapes which are discontinuous with respect to each other. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.