Patents by Inventor Chih-Chiang Chang

Chih-Chiang Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200276123
    Abstract: The present invention provides methods of treating arthritis. A sustained release composition comprising liposomes and one or more therapeutic agent or a pharmaceutically acceptable salt thereof is administered to a subject in need thereof. The liposomes may be in an aqueous suspension. The sustained release composition can be administered intraarticularly.
    Type: Application
    Filed: May 15, 2020
    Publication date: September 3, 2020
    Inventors: KEELUNG HONG, LUKE S. S. GUO, YUN-LONG TSENG, SHEUE-FANG SHIH, PO-CHUN CHANG, CHIH-CHIANG TSAI, HONG-HUI LIN
  • Publication number: 20200271873
    Abstract: In an embodiment, a package structure including an electro-optical circuit board, a fanout package disposed over the electro-optical circuit board is provided. The electro-optical circuit board includes an optical waveguide. The fanout package includes a first optical input/output portion, a second optical input/output portion and a plurality of electrical input/output terminals electrically connected to the electro-optical circuit board. The first optical input/output portion is optically coupled to the second optical input/output portion through the optical waveguide of the electro-optical circuit board.
    Type: Application
    Filed: February 21, 2019
    Publication date: August 27, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Lun Chang, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Hsuan-Ting Kuo, Chia-Shen Cheng, Chih-Chiang Tsao
  • Publication number: 20200257326
    Abstract: A bandgap reference circuit includes a current generating circuit, a switch circuit and a control circuit. The current generating circuit is triggered by a trigger signal, generated when the bandgap reference circuit starts up, to mirror a base current to generate a first current and a second current. The current generating circuit is arranged to output the first current when triggered by the triggered signal. The switch circuit is controlled by a switch control signal to be selectively coupled between the current generating circuit and a terminal coupled to a regulator. The switch circuit is arranged to, when coupled between the current generating circuit and the terminal, allow the current generating circuit to output the second current to the terminal and accordingly provide a bandgap voltage. When the first current reduces to a predetermined level, the control circuit activates generation of the switch control signal to control the switch circuit.
    Type: Application
    Filed: April 30, 2020
    Publication date: August 13, 2020
    Inventors: NAI CHEN CHENG, CHUNG-CHIEH YANG, CHIH-CHIANG CHANG, YUNG-CHOW PENG
  • Patent number: 10736846
    Abstract: The present invention provides methods of treating arthritis. A sustained release composition comprising liposomes and one or more therapeutic agent or a pharmaceutically acceptable salt thereof is administered to a subject in need thereof. The liposomes may be in an aqueous suspension. The sustained release composition can be administered intraarticularly.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: August 11, 2020
    Assignees: TAIWAN LIPOSOME CO., LTD., TCL BIOPHARMACEUTICALS, INC.
    Inventors: Keelung Hong, Luke S. S. Guo, Yun-Long Tseng, Sheue-Fang Shih, Po-Chun Chang, Chih-Chiang Tsai, Hong-Hui Lin
  • Patent number: 10727131
    Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain regions with the incorporation of a lateral etch in the epitaxial source/drain growth process. For example, the method can include forming a plurality of fins on a substrate, where each of the plurality of fins has a first width. The SiGe source/drain regions can be formed on the plurality of fins, where each SiGe source/drain region has a second width in a common direction with the first width and a height. The method can also include selectively etching—e.g., via a lateral etch—the SiGe source/drain regions to decrease the second width of the SiGe source/drain regions. By decreasing the width of the SiGe source/drain regions, electrical shorts between neighboring fins can be prevented or minimized. Further, the method can include growing an epitaxial capping layer over the Si/Ge source/drain regions.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kun-Mu Li, Chih-Chiang Chang, Wen-Chu Hsiao, Che-Yu Lin, Wei-Siang Yang
  • Patent number: 10714376
    Abstract: The present disclosure relates to methods for forming fill materials in trenches having different widths and related structures. A method may include: forming a first fill material in a first and second trench where the second trench has a greater width than the first trench; removing a portion of the first fill material from each trench and forming a second fill material over the first fill material; removing a portion of the first and second fill material within the second trench; and forming a third fill material in the second trench. The structure may include a first fill material in trenches having different widths wherein the upper surfaces of the first fill material in each trench are substantially co-planar. The structure may also include a second fill material on the first fill material in each trench, the second fill material having a substantially equal thickness in each trench.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: July 14, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chih-Chiang Chang, Haifeng Sheng, Jiehui Shu, Haigou Huang, Pei Liu, Jinping Liu, Haiting Wang, Daniel J. Jaeger
  • Patent number: 10713521
    Abstract: An image capturing apparatus including a substrate, a light source, a sensor, a light shielding element, a first reflective element, and a transparent colloid curing layer is provided. The light source, the sensor, the light shielding element, the first reflective element, and the transparent colloid curing layer are disposed on the substrate. The sensor is located next to the light source. The light shielding element is located between the light source and the sensor. The first reflective element is located between the light shielding element and the sensor. The transparent colloid curing layer covers the light source, the sensor, the light shielding element, and the first reflective element. A manufacturing method of the image capturing apparatus is also provided.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 14, 2020
    Assignee: Gingy Technology Inc.
    Inventors: Kuo-Liang You, Kuo-Wen Yang, Cheng-Jyun Huang, Yu-Cheng Chiu, Hao-Hsiang Chang, Chih-Chiang Yu
  • Publication number: 20200152616
    Abstract: A manufacturing method of a package-on-package structure includes at least the following steps. A plurality of conductive bumps of a first package is attached to a tape carrier. A second package is coupled to the first package opposite to the plurality of conductive bumps. When coupling the second package, the plurality of conductive bumps are deformed to form a plurality of deformed conductive bumps, and a contact area between the tape carrier and the respective deformed conductive bump increases.
    Type: Application
    Filed: January 12, 2020
    Publication date: May 14, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsuan-Ting Kuo, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Hao-Jan Pei, Yu-Peng Tsai, Chia-Lun Chang, Chih-Chiang Tsao, Philip Yu-Shuan Chung
  • Patent number: 10649482
    Abstract: A bandgap reference circuit includes a current generating circuit, a switch circuit and a control circuit. The current generating circuit is triggered by a trigger signal generated when the bandgap reference circuit starts up. The current generating circuit is arranged to generate a reference current according to the trigger signal. The switch circuit is controlled by a switch control signal to be selectively coupled between the current generating circuit and a regulator. The switch circuit is arranged to, when coupled between the current generating circuit and the regulator according to the switch control signal, provide a bandgap voltage to the regulator according to the reference current. The control circuit is coupled to the current generating circuit and the switch circuit, and is arranged to generate the switch control signal according to the trigger signal.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Nai Chen Cheng, Chung-Chieh Yang, Chih-Chiang Chang, Yung-Chow Peng
  • Publication number: 20200133061
    Abstract: A polarizer substrate includes a substrate, an organic planarization layer, an inorganic buffer layer, and a plurality of strip-shaped polarizer structures. The organic planarization layer is located on the substrate. The inorganic buffer layer is located on the organic planarization layer. The inorganic buffer layer has a plurality of trenches located on a first surface. The trenches do not penetrate through the inorganic buffer layer. The strip-shaped polarizer structures are located on the first surface of the inorganic buffer layer. Each of the trenches is located between two adjacent polarizer structures. A display panel is also provided.
    Type: Application
    Filed: May 9, 2019
    Publication date: April 30, 2020
    Applicant: Au Optronics Corporation
    Inventors: Tsai-Sheng Lo, Chih-Chiang Chen, Ming-Jui Wang, Sheng-Kai Lin, Sheng-Ming Huang, Chia-Hsin Chung, Hui-Ku Chang, Wei-Chi Wang, Jen-Kuei Lu
  • Patent number: 10636890
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to chamfered replacement gate structures and methods of manufacture. The structure includes: a recessed gate dielectric material in a trench structure; a plurality of recessed workfunction materials within the trench structure on the recessed gate dielectric material; a plurality of additional workfunction materials within the trench structure and located above the recessed gate dielectric material and the plurality of recessed workfunction materials; a gate metal within the trench structure and over the plurality of additional workfunction materials, the gate metal and the plurality of additional workfunction materials having a planar surface below a top surface of the trench structure; and a capping material over the gate metal and the plurality of additional workfunction materials.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: April 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Rongtao Lu, Chih-Chiang Chang, Guowei Xu, Hui Zang, Scott Beasor, Ruilong Xie
  • Publication number: 20200125128
    Abstract: A bandgap reference circuit includes a current generating circuit, a switch circuit and a control circuit. The current generating circuit is triggered by a trigger signal generated when the bandgap reference circuit starts up. The current generating circuit is arranged to generate a reference current according to the trigger signal. The switch circuit is controlled by a switch control signal to be selectively coupled between the current generating circuit and a regulator. The switch circuit is arranged to, when coupled between the current generating circuit and the regulator according to the switch control signal, provide a bandgap voltage to the regulator according to the reference current. The control circuit is coupled to the current generating circuit and the switch circuit, and is arranged to generate the switch control signal according to the trigger signal.
    Type: Application
    Filed: July 8, 2019
    Publication date: April 23, 2020
    Inventors: NAI CHEN CHENG, CHUNG-CHIEH YANG, CHIH-CHIANG CHANG, YUNG-CHOW PENG
  • Publication number: 20200105624
    Abstract: A semiconductor device includes a first source/drain feature adjoining first nanostructures, and a first multilayer work function structure surrounding the first nanostructures. The first multilayer work function structure includes a first middle dielectric layer around the first nanostructures and a first metal layer around and in contact with the first middle dielectric layer. The semiconductor device also includes a second source/drain feature adjoining second nanostructures, and a second multilayer work function structure surrounding the second nanostructures. The second multilayer work function structure includes a second middle dielectric layer around the second nanostructures and a second metal layer around and in contact with the second middle dielectric layer. The first middle dielectric layer and the second middle dielectric layer are made of dielectric materials. The second metal layer and the first metal layer are made of the same metal material.
    Type: Application
    Filed: December 2, 2019
    Publication date: April 2, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Sheng CHEN, Tzu-Chiang CHEN, Cheng-Hsien WU, Chih-Chieh YEH, Chih-Sheng CHANG
  • Publication number: 20200106156
    Abstract: An electronic device and a manufacturing method thereof are provided. The electronic device includes a chip package, an antenna pattern, and an insulating layer. The chip package includes a semiconductor die and an insulating encapsulation enclosing the semiconductor die. The antenna pattern is electrically coupled to the chip package, where a material of the antenna pattern comprises a conductive powder having fused metal particles. The insulating layer disposed between the chip package and the antenna pattern, where the antenna pattern includes a first surface in contact with the insulating layer, and a second surface opposite to the first surface, and a surface roughness of the second surface is greater than a surface roughness of the first surface.
    Type: Application
    Filed: April 18, 2019
    Publication date: April 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Lin Lu, Hsiu-Jen Lin, Hsuan-Ting Kuo, Kai-Chiang Wu, Ming-Che Ho, Wei-Yu Chen, Yu-Peng Tsai, Chia-Lun Chang, Chia-Shen Cheng, Chih-Chiang Tsao, Tzu-Chun Tang, Ching-Hua Hsieh, Tuan-Yu Hung, Cheng-Shiuan Wong
  • Publication number: 20200103572
    Abstract: A polarizer substrate and manufacturing method thereof are provided. The polarizer substrate includes a substrate, a plurality of polarizer structures, a plurality of barrier structures, and a passivation layer. The polarizer structures are disposed on the substrate. Each of the polarizer structures includes a wire-grid and a capping structure disposed on the wire-grid. The barrier structures are disposed on the capping structures and not contacting with the side walls of the wire-grids. A gap between two adjacent barrier structures is smaller than a gap between two adjacent wire-grids. The passivation layer is disposed on the barrier structures.
    Type: Application
    Filed: May 14, 2019
    Publication date: April 2, 2020
    Applicant: Au Optronics Corporation
    Inventors: Wei-Chi Wang, Chih-Chiang Chen, Tsai-Sheng Lo, Sheng-Kai Lin, Chia-Hsin Chung, Hui-Ku Chang, Ming-Jui Wang, Sheng-Ming Huang, Jen-Kuei Lu
  • Publication number: 20200066587
    Abstract: A method for forming a semiconductor device structure includes providing a substrate and forming a gate electrode on the substrate. A first contact structure is formed in and on the gate electrode. The first contact structure comprises a first portion and a second portion. The first portion is formed in the gate electrode, and the second portion is formed on the first portion.
    Type: Application
    Filed: November 4, 2019
    Publication date: February 27, 2020
    Inventors: Guo-Chiang CHI, Chia-Der CHANG, Chih-Hung LU, Wei-Chin CHEN
  • Patent number: 10566261
    Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: February 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Jan Pei, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Cheng-Ting Chen, Chia-Lun Chang, Chih-Wei Lin, Hsiu-Jen Lin, Ching-Hua Hsieh, Chung-Shi Liu
  • Publication number: 20200052106
    Abstract: At least one method, apparatus, and system providing semiconductor devices comprising a first gate having a first width and comprising a first work function metal (WFM); a first liner disposed over the first WFM; a first gate metal having a first height; and a first pinch-off spacer over the first WFM, the first liner, and the first gate metal to above the first height; and a second gate having a second width greater than the first width, and comprising a second WFM; a second liner disposed over the second WFM; a second gate metal having substantially the first height; and a first conformal spacer over the second WFM and the second liner.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 13, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Laertis Economikos, Hui Zang, Ruilong Xie, Neal Makela, Pei Liu, Jiehui Shu, Chih-chiang Chang
  • Patent number: 10535644
    Abstract: A manufacturing method of a package on package structure includes the following steps. A first package is provided on a tape carrier, wherein the first package includes an encapsulated semiconductor device, a first redistribution structure disposed on a first side of the encapsulated semiconductor device, and a plurality of conductive bumps disposed on the first redistribution structure and attached to the tape carrier. A second package is mounted on the first package through a plurality of electrical terminals by a thermo-compression bonding process, which deforms the conductive bumps into a plurality of deformed conductive bumps. Each of the deformed conductive bumps comprises a base portion connecting the first redistribution structure and a tip portion connecting the base portion, and a curvature of the base portion is substantially smaller than a curvature of the tip portion.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsuan-Ting Kuo, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Hao-Jan Pei, Yu-Peng Tsai, Chia-Lun Chang, Chih-Chiang Tsao, Philip Yu-shuan Chung
  • Publication number: 20200013881
    Abstract: Examples of an integrated circuit and a method for forming the integrated circuit are provided herein. In some examples, a method includes receiving a substrate that includes: a plurality of fins extending above a remainder of the substrate; a first region that includes a first fence region that contains a first subset of the plurality of fins; and a second region that includes a second fence region that contains a second subset of the plurality of fins. The first region has a first performance characteristic, and the second region has a second performance characteristic that is different from the first. Based on the first performance characteristic, the first subset of the plurality of fins is recessed to a first height, and based on the second performance characteristic, the second subset of the plurality of fins is recessed to a second height that is less than the first height.
    Type: Application
    Filed: August 26, 2019
    Publication date: January 9, 2020
    Inventors: Che-Cheng Chang, Chih-Han Lin, Wei-Chiang Hung, Wei-Hao Huang