Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. After the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.

Abstract: An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a first intermetal dielectric (IMD) layer disposed over a plurality of conductive features and a first passive component disposed on the first IMD layer in a first region of the substrate. The structure further includes a second passive component disposed on the first IMD layer in a second region of the substrate. The second passive component includes a first conductive layer, and the first conductive layer has a first thickness. The structure further includes a second IMD layer disposed on the first passive component in the first region and on the second passive component and a portion of the first IMD layer in the second region. The second IMD layer has a second thickness ranging from about five times to about 20 times the first thickness.

Abstract: A circuit board structure includes a substrate, a first build-up structure layer, first and second external circuit layers, at least one first conductive via, and second conductive vias. The first build-up structure layer is disposed on a first circuit layer of the substrate. The first external circuit layer is disposed on the first build-up structure layer. The second external circuit layer is disposed on a second circuit layer and a portion of a third dielectric layer of the substrate. The first conductive via is electrically connected to the first external circuit layer and the second external circuit layer to define a signal path. The second conductive vias surround the first conductive via, and the first external circuit layer, the second conductive vias, the first circuit layer, the outer conductive layer, and the second external circuit layer define a first ground path. The first ground path surrounds the signal path.

Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.

Abstract: A semiconductor package includes a substrate, a semiconductor device over the substrate and a plurality of solder joint structures bonded between the semiconductor device and the substrate, wherein each of the plurality of solder joint structures includes, by weight percent, 2% to 23% of Indium (In).

Abstract: A semiconductor device includes an active region over a substrate extending along a first lateral direction. The semiconductor device includes a number of first conductive structures operatively coupled to the active region. The first conductive structures extend along a second lateral direction. The semiconductor device includes a number of second conductive structures disposed above the plurality of first conductive structures. The second conductive structures extend along the first lateral direction. The semiconductor device includes a first capacitor having a first electrode and a second electrode. The first electrode includes one of the first conductive structures and the active region, and the second electrode includes a first one of the second conductive structures. Each of the active region and the first conductive structures is electrically coupled to a power rail structure configured to carry a supply voltage.

Abstract: A device for measuring a frequency response of a wafer is provided. The device includes a first oscillator, a clock generator, a first circuit, and a first driver. The first oscillator configured to provide a first signal having a first frequency. The clock generator is configured to receive the first signal and generate a first clock signal and a second clock signal having the first frequency. The first circuit on the wafer and having a first number of parallelly connected ring oscillators. The first driver is coupled to the first circuit and the clock generator, and configured to receive the first clock signal and the second clock signal, and drive the first circuit. A first portion of each ring oscillator of the first circuit is electrically disconnected from a second portion of each ring oscillator of the first circuit.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain (S/D) feature disposed in a recess between two adjacent channel regions, wherein the S/D feature comprises an epitaxial layer conformally deposited on an exposed surface of the recess. The structure also includes a silicide layer conformally disposed on the S/D feature, and a S/D contact disposed on the silicide layer, wherein the S/D contact has a first portion extending into the recess, and the first portion has at least three surfaces being surrounded by the silicide layer and the S/D feature.

Abstract: Systems and methods are described herein for charge-based capacitor measurement. The system includes a first pseudo-inverter circuit and a second pseudo-inverter circuit. The system also includes a control circuit coupled between the first inverter circuit and the second inverter circuit. The control circuit is configured to generate independent and non-overlapping control signals for the first pseudo-inverter circuit and the second pseudo-inverter circuit. A shielding metal is coupled to the first pseudo-inverter circuit, the second pseudo-inverter circuit, and the control circuit. The shielding metal is configured to dissipate parasitic capacitance of at least one of the first pseudo-inverter circuit or the second pseudo-inverter circuit. A device under test is coupled to each of the first inverter circuit and the second inverter circuit.

Abstract: A device including an inverter circuit, a hysteresis control circuit, and a high-side input level shifter. The inverter circuit having an output and including at least two series connected PMOS transistors connected, at the output, in series to at least two series connected NMOS transistors. The hysteresis control circuit coupled to the output to provide feedback to the at least two series connected PMOS transistors and to the at least two series connected NMOS transistors. The high-side input level shifter connected to gates of the at least two PMOS transistors and configured to shift a low level of an input signal to a higher level and provide the higher level to one or more of the gates of the at least two PMOS transistors.

Abstract: A device for measuring characteristics of a wafer is provided. The device includes a first circuit on the wafer and having a first number of parallelly connected oscillators, and a second circuit on the wafer and having the first number of parallelly connected oscillators; wherein a first portion of the second circuit is disconnected from a second portion of the second circuit.

Abstract: Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.

Abstract: A device including an inverter circuit, a hysteresis control circuit, and a high-side input level shifter. The inverter circuit having an output and including at least two series connected PMOS transistors connected, at the output, in series to at least two series connected NMOS transistors. The hysteresis control circuit coupled to the output to provide feedback to the at least two series connected PMOS transistors and to the at least two series connected NMOS transistors. The high-side input level shifter connected to gates of the at least two PMOS transistors and configured to shift a low level of an input signal to a higher level and provide the higher level to one or more of the gates of the at least two PMOS transistors.

Abstract: Disclosed are a laser-treated anti-deposition object with a main structure and a fluorine coating layer and a manufacturing method of the same. The fluorine coating layer covers a laser-treated surface of the main structure to form an anti-deposition surface, an initial surface of the main structure is subjected to a laser surface treatment step by a laser to become the laser-treated surface with a plurality of microstructures. The anti-deposition object contacts with a manufacturing process substance used or discharged during a manufacturing process performed by a manufacturing process equipment in a vacuum environment, and the anti-deposition surface of the object has a relatively high contact angle.

Abstract: A pellicle includes a frame having an attachment surface configured to attach to a photomask, wherein the frame comprises a vent hole. The pellicle further includes a filter covering the vent hole, wherein the filter directly contacts an inner surface of the frame, and the filter extends in a direction parallel to the attachment surface. The pellicle further includes a membrane extending over a top surface of the frame.

Abstract: A semiconductor package includes a substrate, a semiconductor device over the substrate and a plurality of solder joint structures bonded between the semiconductor device and the substrate, wherein each of the plurality of solder joint structures includes, by weight percent, 2% to 23% of Indium (In).

Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.

Abstract: Systems and methods are described herein for charge-based capacitor measurement. The system includes a first pseudo-inverter circuit and a second pseudo-inverter circuit. The system also includes a control circuit coupled between the first inverter circuit and the second inverter circuit. The control circuit is configured to generate independent and non-overlapping control signals for the first pseudo-inverter circuit and the second pseudo-inverter circuit. A shielding metal is coupled to the first pseudo-inverter circuit, the second pseudo-inverter circuit, and the control circuit. The shielding metal is configured to dissipate parasitic capacitance of at least one of the first pseudo-inverter circuit or the second pseudo-inverter circuit. A device under test is coupled to each of the first inverter circuit and the second inverter circuit.

Abstract: A manufacturing method of a package-on-package structure includes placing a lower package on a tape, where conductive bumps of the lower package are in contact with the tape; and bonding an upper package to the lower package, where during the bonding, the conductive bumps are pressed against the tape so that a curvature of the respective conductive bump changes.

Abstract: The present disclosure provides a circuitry. The circuitry includes a comparator, a signal correlated circuit, and a receiver unit. The comparator includes a first input terminal, a second input terminal, and an output terminal. The signal correlated circuit is configured to receive a first input signal and a second input signal independent from the first input signal. The signal correlated circuit is configured to generate a first output signal and to send the first output signal to the first input terminal of the comparator, and configured to generate a second output signal and to send the second output signal to the second input terminal of the comparator. The receiver unit is connected to the output terminal of the comparator and configured to generate a feedback signal in response to an output signal of the comparator, wherein the first and second digital signals are adjusted based on the feedback signal.