Abstract: A display system including a driving circuit and a display panel is disclosed. The display panel displays an image according to the data signals and the scan signals and includes a first driving unit, a second driving unit, a first luminous element, a second luminous element and a third luminous element. The first driving unit includes a first driving transistor to generate a first driving current. The second driving unit includes a second driving transistor to generate a second driving current. The first luminous element is lighted according to the first driving current when a first emitting signal is activated. The second luminous element is lighted according to the first driving current when a second emitting signal is activated. The third luminous element is lighted according to the second driving current when the first emitting signal is activated.

Abstract: A pixel structure including a first switching transistor, a setting unit, a capacitor, a driving transistor, a second switching transistor and a luminous element is disclosed. The capacitor is coupled between a first and a second node. The first switching transistor transmits a data signal to the first node according to a scan signal. The driving transistor includes a threshold voltage and a gate coupled to the second node. The second switching transistor includes a gate receiving an emitting signal. The luminous element is coupled to the driving transistor and the second switching transistor in series between a first operation voltage and a second operation voltage. The setting unit controls the voltage levels of the first and the second nodes to compensate the threshold voltage of the driving transistor.

Abstract: A slurry feed system suitable for chemical mechanical planarization (CMP) processes in a semiconductor fabrication facility and related method. The slurry feed system includes a valve manifold box having a discharge piping header fluidly connected to at least one CMP station and a first slurry supply train. The first slurry supply train may include a slurry mixing tank, day tank, and at least two slurry feed pumps arranged in series pumping relationship. The first slurry supply train defines a first slurry piping loop. In one embodiment, a second slurry supply train defining a second slurry piping loop is provided. The valve manifold box is operable to supply slurry from either or both of the first and second slurry piping loops to the CMP station.

Abstract: A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the selected prefabricated elements is customized. The probe card assembly is then built using the selected and customized elements.

Abstract: A slurry feed system suitable for chemical mechanical planarization (CMP) processes in a semiconductor fabrication facility and related method. The slurry feed system includes a valve manifold box having a discharge piping header fluidly connected to at least one CMP station and a first slurry supply train. The first slurry supply train may include a slurry mixing tank, day tank, and at least two slurry feed pumps arranged in series pumping relationship. The first slurry supply train defines a first slurry piping loop. In one embodiment, a second slurry supply train defining a second slurry piping loop is provided. The valve manifold box is operable to supply slurry from either or both of the first and second slurry piping loops to the CMP station.

Abstract: A combined input and termination circuit comprises a fixed portion of impedance and a programmable portion of impedance. The fixed portion is able to be fixed in a driver mode and a termination mode. The programmable portion is able to be configured to have a desired impedance in a driver mode or a termination mode while maintaining minimum associated capacitance.

Abstract: A combined input and termination circuit comprises a fixed portion of impedance and a programmable portion of impedance. The fixed portion is able to be fixed in a driver mode and a termination mode. The programmable portion is able to be configured to have a desired impedance in a driver mode or a termination mode while maintaining minimum associated capacitance.

Abstract: Bandwidth of a test channel is determined from a single port Time Domain Reflectometer (TDR) measurement with the channel terminated in a short or an open circuit. Bandwidth is estimated by: (1) making a TDR measurement of a channel terminated in a short or open circuit; (2) determining a maximum slope of the reflection from the TDR measurement; (2) calculating an interpolated rise or fall time, for example by taking 80% of the applied voltage between the 10% and 90% points, and then dividing the applied voltage by the maximum slope determined; (3) dividing the overall interpolated rise time by the square root of two to account for the TDR signal proceeding through the channel twice; (4) removing the contribution of rise time from measurement equipment; and (5) completing calculation of channel bandwidth using a formula to relate bandwidth to rise time, such as: bandwidth=0.35/rise time.

Abstract: Bandwidth of a test channel is determined from a single port Time Domain Reflectometer (TDR) measurement with the channel terminated in a short or an open circuit. Bandwidth is estimated by: (1) making a TDR measurement of a channel terminated in a short or open circuit; (2) determining a maximum slope of the reflection from the TDR measurement; (3) calculating an interpolated rise or fall time, for example by taking 80% of the applied voltage between the 10% and 90% points, and then dividing the applied voltage by the maximum slope determined; (4) dividing the overall interpolated rise time by the square root of two to account for the TDR signal proceeding through the channel twice; (5) removing the contribution of rise time from measurement equipment; and (6) completing calculation of channel bandwidth using a formula to relate bandwidth to rise time, such as: bandwidth=0.35/rise time.

Abstract: An integrated circuit comprises a double frequency clock generator and a double input generator to test semiconductor devices at frill frequency using a half frequency tester. A clock generator circuit and a test data generator circuit provides differential clock and test data signals at a normal (1× mode) and high-speed rate (2× mode) to a device under test. In 1× mode, clock generator and test data generator circuits pass through the differential clock signals and test data values provided by a testing device unchanged. In 2× mode, the clock generator circuit receives the differential clock signal as clock signals clk and clkb and outputs clock signals clk_int and clkb_int that are inverted signals and twice the frequency of clk and clkb. The test data generator circuit clocks test data values into registers according to clk_int and clkb_int to generate an increased number of test data values per clock signal clk.

Abstract: A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the selected prefabricated elements is customized. The probe card assembly is then built using the selected and customized elements.

Abstract: A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the selected prefabricated elements is customized. The probe card assembly is then built using the selected and customized elements.

Abstract: A decoding signal circuit is configured to generate a dual operation decoding signal that enables a read operation and a write operation to be performed in one clock cycle. The decoding signal circuit is configured such that a read decoding signal and a write decoding signal are generated and multiplexed together to form the dual operation decoding signal. The memory device receives a read address and a write address consecutively in one cycle to generate the dual operation decoding signal. A single operation, such as a read only operation or a write only operation, can be performed as well as the dual operation of performing the read operation and the write operation in the same cycle.

Abstract: An integrated circuit includes a double frequency clock generator and a double input generator to test semiconductor devices at full frequency using a half frequency tester. A clock generator circuit and a test data generator circuit provides differential clock signals and test data signals at a normal rate (1× mode) and a high speed rate (2× mode) to a device under test. In the 1× mode, the clock generator circuit and the test data generator circuit pass through the differential clock signals and test data values provided by a testing device unchanged. In the 2× mode, the clock generator circuit receives the differential clock signal as a clock signal clk and a clock signal clkb 90 degrees out of phase, and outputs a clock signal clk_int and a clock signal clkb_int that are inverted signals of each other and that are twice the frequency of the clock signal clk and the clock signal clkb.

Abstract: A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the selected prefabricated elements is customized. The probe card assembly is then built using the selected and customized elements.

Abstract: A decoding signal circuit is configured to generate a dual operation decoding signal that enables a read operation and a write operation to be performed in one clock cycle. The decoding signal circuit is configured such that a read decoding signal and a write decoding signal are generated and multiplexed together to form the dual operation decoding signal. The memory device receives a read address and a write address consecutively in one cycle to generate the dual operation decoding signal. A single operation, such as a read only operation or a write only operation, can be performed as well as the dual operation of performing the read operation and the write operation in the same cycle.

Abstract: A contact resistance measuring circuit is configured to determine the contact resistance of a testing device. The measuring circuit is coupled to a processing circuit and the testing device. The measuring circuit includes a pair of input/output units coupled together via a pass device. Each of the input/output units includes a pull-up device and a pull-down device to provide separate pull-up and pull-down control, respectively. The pull-up devices, the pull-down devices, and the pass device are dynamically configurable such that the measuring circuit uses either a pull-up mode or a pull-down mode to measure voltage and current characteristics of each contact point, or pin, of the testing device. The processing circuit calculates the contact resistance for each pin according to the measured voltage and current characteristics. The calculated contact resistances are used to calibrate the testing device.

Abstract: A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the selected prefabricated elements is customized. The probe card assembly is then built using the selected and customized elements.

Abstract: A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the selected prefabricated elements is customized. The probe card assembly is then built using the selected and customized elements.

Abstract: A probe system for providing signal paths between an integrated circuit (IC) tester and input/output, power and ground pads on the surfaces of ICs to be tested includes a probe board assembly, a flex cable and a set of probes arranged to contact the IC's I/O pads. The probe board assembly includes one or more rigid substrate layers with traces and vias formed on or within the substrate layers providing relatively low bandwidth signal paths linking the tester to probes accessing some of the IC's pads. The flex cable provides relatively high bandwidth signal paths linking the tester to probes accessing others of the IC's pads. A flex strip may alternatively be disposed behind a substrate with probes.