Abstract: A bidirectional voltage conversion device includes a first half-bridge switching circuit, a transformer, a first resonant capacitor, a double-pole double-throw relay, a second half-bridge switching circuit, a resonant inductor and a second resonant capacitor. The first half-bridge switching circuit is coupled to a high-voltage power storage device. The first resonant capacitor is coupled to the first half-bridge switching circuit and a primary winding. The double-pole double-throw relay is coupled to a first secondary winding, a second secondary winding and a grounding terminal. The second half-bridge switching circuit is coupled to a low-voltage power storage device. The resonant inductor and the second resonant capacitor are coupled in series between the second half-bridge switching circuit and a node between the first secondary winding and the second secondary winding.

Abstract: The invention provides a semiconductor structure with a deep trench capacitor structures, which comprises a substrate, the substrate comprises a bottle-shaped trench, wherein the bottle-shaped trench has an upper part and a lower part in a cross section, and the interface between the upper part and the lower part is a bottleneck line, wherein the bottleneck line is the part with the smallest width in the bottle-shaped trench, a first dielectric layer is filled in the bottle-shaped trench, and a void is located in the first dielectric layer, wherein the highest point of the void is lower than the bottleneck line.

Abstract: A MIM capacitor structure includes a semiconductor substrate, and a first trench and a second trench in the semiconductor substrate in a capacitance forming region. The second trench is adjacent to the first trench. The second trench is deeper than the first trench. A dielectric liner layer conformally covers a top surface of the semiconductor substrate and interior surfaces of the first trench and the second trench. A bottom electrode layer conformally covers the dielectric liner layer. The bottom electrode layer extends onto a top surface of the semiconductor substrate. A capacitor dielectric layer is disposed on the bottom electrode layer in the first trench and the second trench. A top electrode layer is disposed on the capacitor dielectric layer in the first trench and the second trench. The top surface of the top electrode layer is coplanar with the top surface of the bottom electrode layer.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

Abstract: A semiconductor includes a substrate. A gate structure is disposed on the substrate. A liner oxide contacts a side of the gate structure. A silicon oxide spacer contacts the liner oxide. An end of the silicon oxide spacer forms a kink profile. A silicon nitride spacer contacts the silicon oxide spacer and a tail of the silicon nitride spacer covers part of the kink profile. A stressor covers the silicon nitride spacer and the substrate.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

Abstract: The present disclosure provides a fast charging driver. The fast charging driver is configured to charge a battery of an electronic device. The fast charging driver includes a fast charging circuit and a charging controller. The fast charging circuit includes a first depletion-type GaN transistor, a first enhancement-type field effect transistor, a second depletion-type GaN transistor and a second enhancement-type field effect transistor. The charging controller is configured to control the fast charging circuit to operate in a constant current mode or a constant voltage mode according to a battery level of the battery. By utilizing the first depletion-type GaN transistor and the second depletion-type GaN transistor with a characteristic of a relatively low switching loss, the power consumption during charging the battery by the fast charging driver is decreased to improve the charge speed.

Abstract: The disclosure provides an abnormal current monitoring device and an abnormal current monitoring method. The abnormal current monitoring device includes a first detection circuit which detects a first electrical parameter of a power device based on an i-th level short circuit time, a second detection circuit which detects a second electrical parameter of the power device to generate an i-th level detection signal based on the i-th level short circuit time, and a control circuit which generates an i-th level heat estimation value to determine whether the power device is damaged according to the first electrical parameter, and determines whether the power device is abnormal in operation according to the i-th level detection signal, so as to record the i-th level heat estimation value and the i-th level short circuit time, or adjust the i-th level short circuit time to an i+1-th level short circuit time.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

Abstract: The disclosure provides a power control device, which comprises a bleeder circuit forming a first discharging path and an aux low-voltage (LV) power supply unit forming a second discharging path. The bleeder circuit is connected with a voltage-regulating capacitor stably maintaining the high-voltage (HV) level from a HV battery. The aux LV power supply unit is connected with the bleeder circuit and the voltage-regulating capacitor in parallel. The aux LV power supply unit provides an aux LV level to the driver, when the power system operates abnormally, the HV level is discharged through the first and second discharging path and/or a third discharging path formed by a driver and a motor.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.

Abstract: A D-mode GaN transistor synchronous rectifier of the present invention includes a power switching module, a peak detection module, and a gate driver module. The peak detection module stores energy when the negative end of the secondary side winding of the power converter is at a high voltage. The power switching module includes a first switch and a D-mode GaN HEMT as a second switch connected in series. The energy is provided to the module gate of the power switching module through the gate driver module to keep the first switch turned on. The gate driver module conducts the module gate and the module source when the positive end of the secondary side winding is at a low voltage, such that a clamp circuit pulls the gate-source voltage of the second switch below threshold and turns it off. The synchronous rectifier replaces conventional diode rectifier, having lower conduction loss and response ringing.

Abstract: A semiconductor device includes a gate structure on a substrate and an epitaxial layer adjacent to the gate structure, in which the epitaxial layer includes a first buffer layer, an anisotropic layer on the first buffer layer, a second buffer layer on the first buffer layer, and a bulk layer on the anisotropic layer. Preferably, a concentration of boron in the bulk layer is less than a concentration of boron in the anisotropic layer, a concentration of boron in the first buffer layer is less than a concentration of boron in the second buffer layer, and the concentration of boron in the second buffer layer is less than the concentration of boron in the anisotropic layer.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.

Abstract: The disclosure provides an abnormal current monitoring device and an abnormal current monitoring method. The abnormal current monitoring device includes a first detection circuit which detects a first electrical parameter of a power device based on an i-th level short circuit time, a second detection circuit which detects a second electrical parameter of the power device to generate an i-th level detection signal based on the i-th level short circuit time, and a control circuit which generates an i-th level heat estimation value to determine whether the power device is damaged according to the first electrical parameter, and determines whether the power device is abnormal in operation according to the i-th level detection signal, so as to record the i-th level heat estimation value and the i-th level short circuit time, or adjust the i-th level short circuit time to an i+1-th level short circuit time.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.