Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

Abstract: A voltage-controlled varied frequency pulse width modulator is provided, including a frequency-regulating voltage output device which receives a determining voltage, decides a resonant frequency according to the determining voltage and outputs an oscillation signal having the resonant frequency. A duty-ratio-regulating voltage output device receives the oscillation signal and a reference signal to determine a duty ratio through an inverting closed loop, so as to adjust the oscillation signal to have the duty ratio. By employing the proposed voltage-controlled modulator circuit with tunable frequency and varied pulse width of the present invention, a modulation signal having the determined resonant frequency and duty ratio is obtained. Moreover, the present invention can be further combined with gate drive waveform trend feedback designs to achieve superior power transmission efficiency of a wireless power transmission system to optimize the inventive effect of the present invention.

Abstract: An operation method and an operation device of a motor driver for driving a motor are provided. The operation method includes: establishing a hysteresis control method; and adjusting a switch frequency of a power module for operating the motor by using the hysteresis control method according to a change of rotation speed of the motor and a current switch frequency.

Abstract: An operation method and an operation device of a motor driver for driving a motor are provided. The operation method includes: establishing a hysteresis control method; and adjusting a switch frequency of a power module for operating the motor by using the hysteresis control method according to a change of rotation speed of the motor and a current switch frequency.

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

Abstract: A semiconductor device includes a substrate having a first region and a second region and a gate structure on the first region and the second region of the substrate. The gate structure includes a first bottom barrier metal (BBM) layer on the first region and the second region, a first work function metal (WFM) layer on the first region; and a diffusion barrier layer on a top surface and a sidewall of the first WFM layer on the first region and the first BBM layer on the second region. Preferably, a thickness of the first BBM layer on the second region is less than a thickness of the first BBM layer on the first region.

Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.

Abstract: Apparatus and method for monitoring wafer charges are proposed. A conductive pin, a conductive spring and a conductive line are configured in series to connect the backside surface of the wafer and the sample conductor so that the backside surface of the wafer and the surface of the sample conductor have identical charge density. Hence, by using a static electricity sensor positioned close to the surface of the sample conductor, the charges on the wafer may be monitored. Note that the charges appeared on the frontside surface of the wafer induces charges on the backside surface of the wafer. The sample conductor is a sheet conductor and properly insulated from the surrounding environment. As usual, the sample conductor and the static electricity sensor are positioned outside the chamber where the wafer is placed and processed, so as to simplify the apparatus inside the chamber and reduce the contamination risk.

Abstract: A high power module is provided, which includes a substrate, plural first power chips, plural second power chips, a positive electrode plate and a negative electrode plat. The substrate includes a first metal area, a second metal area, a third metal area disposed between the first metal area and the second metal area. The first power chips are disposed on the third metal area and connected to the first metal area via plural first connection elements. The second power chips are disposed on the second metal area and connected to the third metal area via plural second connection elements. The positive electrode plate is C-shaped and connected to the first metal area. The negative electrode plate is C-shaped and connected to the second metal area; the direction of the opening of the negative electrode plate is contrary to that of the opening of the positive electrode plate.

Abstract: A semiconductor device includes an insulating thermal substrate, a metal wiring layer and a heat-dissipation component. The metal wiring layer includes a plurality of engaging structures. The plurality of engaging structures is disposed between the insulating thermal substrate and the heat-dissipation component, and the heat-dissipation component applies solder structures to connect the metal wiring layer by having the solder structures to wrap partly the plurality of engaging structures. In addition, a method for fabricating the same semiconductor device is also provided.

Abstract: A semiconductor device includes a substrate having a first region and a second region and a gate structure on the first region and the second region of the substrate. The gate structure includes a first bottom barrier metal (BBM) layer on the first region and the second region, a first work function metal (WFM) layer on the first region; and a diffusion barrier layer on a top surface and a sidewall of the first WFM layer on the first region and the first BBM layer on the second region. Preferably, a thickness of the first BBM layer on the second region is less than a thickness of the first BBM layer on the first region.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first bottom barrier metal (BBM) layer on the first region and the second region; forming a first work function metal layer on the first BBM layer on the first region and the second region; removing the first work function metal (WFM) layer and part of the first BBM layer on the second region; and forming a diffusion barrier layer on the first WFM layer on the first region and the first BBM layer on the second region.

Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first bottom barrier metal (BBM) layer on the first region and the second region; forming a first work function metal layer on the first BBM layer on the first region and the second region; removing the first work function metal (WFM) layer and part of the first BBM layer on the second region; and forming a diffusion barrier layer on the first WFM layer on the first region and the first BBM layer on the second region.

Abstract: Apparatus and method for monitoring wafer charges are proposed. A conductive pin, a conductive spring and a conductive line are configured in series to connect the backside surface of the wafer and the sample conductor so that the backside surface of the wafer and the surface of the sample conductor have identical charge density. Hence, by using a static electricity sensor positioned close to the surface of the sample conductor, the charges on the wafer may be monitored. Note that the charges appeared on the frontside surface of the wafer induces charges on the backside surface of the wafer. The sample conductor is a sheet conductor and properly insulated from the surrounding environment. As usual, the sample conductor and the static electricity sensor are positioned outside the chamber where the wafer is placed and processed, so as to simplify the apparatus inside the chamber and reduce the contamination risk.

Abstract: A structure of semiconductor device includes a gate structure, disposed on a substrate. A spacer is disposed on a sidewall of the gate structure, wherein the spacer is an l-like structure. A first doped region is disposed in the substrate at two sides of the gate structure. A second doped region is disposed in the substrate at the two sides of the gate structure, overlapping the first doped region. A silicide layer is disposed on the substrate within the second doped region, separating from the spacer by a distance. A dielectric layer covers over the second doped region and the gate structure with the spacer.

Abstract: Apparatus and method for monitoring wafer charges are proposed. A conductive pin, a conductive spring and a conductive line are configured in series to connect the backside surface of the wafer and the sample conductor so that the backside surface of the wafer and the surface of the sample conductor have identical charge density. Hence, by using a static electricity sensor positioned close to the surface of the sample conductor, the charges on the wafer may be monitored. Note that the charges appeared on the frontside surface of the wafer induces charges on the backside surface of the wafer. As usual, the sample conductor is a sheet conductor and properly insulated from the surrounding environment. As usual, the sample conductor and the static electricity sensor are positioned outside the chamber where the wafer is placed and processed, so as to simplify the apparatus inside the chamber and reduce the contamination risk.

Abstract: A sinusoidal modulation method and a three-phase inverter are disclosed. A pulse driving signal controller is disposed to connect the three-phase inverter. The pulse driving signal controller controls the transistors of the three-arm full-bridge architecture. By examining the phase angle of the output current, operations of the upper and lower bridge power transistors can be adjusted, so that three power transistors are turned on and the other three power transistors are turned off during the PWM operations. As a result, the dead time is not required to set during the PWM operation for preventing a short-circuit due to dynamic switching errors of the upper and lower bridge power transistors. The requirements of the hardware circuits can be also reduced.

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.