Patents by Inventor Chih-Chiang Wu
Chih-Chiang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230143658Abstract: A power module includes: a GaN transistor, an NMOS transistor, a first capacitor, a first diode and a second diode. The NMOS transistor is electrically connected to the GaN transistor. A negative electrode of the first capacitor is electrically connected to an anode of the first diode and a gate of the GaN transistor. A cathode of the second diode is electrically connected to a gate of the NMOS transistor. The power module further includes a power module control terminal electrically connected to an anode of the first capacitor and an anode of the second diode.Type: ApplicationFiled: January 11, 2022Publication date: May 11, 2023Inventors: Ching-Yao LIU, Yueh-Tsung HSIEH, Kuo-Bin WANG, Chih-Chiang WU, Li-Chuan TANG, Wei-Hua CHIENG, Edward Yi CHANG, Stone CHENG
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Patent number: 11646732Abstract: A power module includes: a GaN transistor, an NMOS transistor, a first capacitor, a first diode and a second diode. The NMOS transistor is electrically connected to the GaN transistor. A negative electrode of the first capacitor is electrically connected to an anode of the first diode and a gate of the GaN transistor. A cathode of the second diode is electrically connected to a gate of the NMOS transistor. The power module further includes a power module control terminal electrically connected to an anode of the first capacitor and an anode of the second diode.Type: GrantFiled: January 11, 2022Date of Patent: May 9, 2023Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Ching-Yao Liu, Yueh-Tsung Hsieh, Kuo-Bin Wang, Chih-Chiang Wu, Li-Chuan Tang, Wei-Hua Chieng, Edward Yi Chang, Stone Cheng
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Publication number: 20230093515Abstract: A synchronous buck converter using a single gate drive control is provided and includes a drive circuit, a p-type gallium nitride (p-GaN) transistor switch module and an inductor. A gallium nitride power transistor is used as an upper side transistor switch, and a PMOS power transistor is used as a lower side transistor switch in the p-GaN transistor switch module. A gate of the upper side transistor switch and a gate of the lower side transistor switch are coupled to each other and receive a switch signal provided by the drive circuit at the same time. By controlling the on and off of the upper side transistor switch and the lower side transistor switch, the problem of simultaneous activation of the upper and lower side transistor switches can be avoided.Type: ApplicationFiled: December 1, 2021Publication date: March 23, 2023Inventors: Wei-Hua Chieng, Edward Yi Chang, Stone Cheng, Shyr-Long Jeng, Li-Chuan Tang, Chih-Chiang Wu, Ching-Yao Liu, Kuo-Bin Wang
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Patent number: 11569696Abstract: A control method of a minimum power input applicable to a wireless power transfer system including a power transmission unit and at least one power receiving unit is provided. The power transmission unit is electrically connected with a control voltage signal and an input voltage signal and accordingly generates the minimum power input. The power transmission unit transmits the minimum power input wirelessly through a wireless transmission to the at least one power receiving unit for receiving. By adjusting the input voltage signal, the duty ratio and resonant frequency of the control voltage signal, the present invention ensures an optimal power transmission efficiency of the wireless power transmission system. Moreover, parameters of a charge pump reservoir and gate driving circuit can be further designed in view of the trend feedback of its gate drive waveforms so as to optimize the effect of the proposed invention.Type: GrantFiled: May 28, 2021Date of Patent: January 31, 2023Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Wei-Hua Chieng, Edward Yi Chang, Stone Cheng, Shyr-Long Jeng, Newton Tang, Chih-Chiang Wu, Ching-Yao Liu, Kuo-Bin Wang
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Publication number: 20230005795Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.Type: ApplicationFiled: August 3, 2021Publication date: January 5, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yi-Fan Li, Po-Ching Su, Yu-Fu Wang, Min-Hua Tsai, Ti-Bin Chen, Chih-Chiang Wu, Tzu-Chin Wu
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Publication number: 20220385093Abstract: The present disclosure provides a fast charging driver. The fast charging driver is configured to charge a battery of an electronic device. The fast charging driver includes a fast charging circuit and a charging controller. The fast charging circuit includes a first depletion-type GaN transistor, a first enhancement-type field effect transistor, a second depletion-type GaN transistor and a second enhancement-type field effect transistor. The charging controller is configured to control the fast charging circuit to operate in a constant current mode or a constant voltage mode according to a battery level of the battery. By utilizing the first depletion-type GaN transistor and the second depletion-type GaN transistor with a characteristic of a relatively low switching loss, the power consumption during charging the battery by the fast charging driver is decreased to improve the charge speed.Type: ApplicationFiled: April 27, 2022Publication date: December 1, 2022Inventors: Edward Yi CHANG, Stone CHENG, Wei-Hua CHIENG, Shyr-Long JENG, Chih-Chiang WU
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Publication number: 20220285999Abstract: A control method of a minimum power input applicable to a wireless power transfer system including a power transmission unit and at least one power receiving unit is provided. The power transmission unit is electrically connected with a control voltage signal and an input voltage signal and accordingly generates the minimum power input. The power transmission unit transmits the minimum power input wirelessly through a wireless transmission to the at least one power receiving unit for receiving. By adjusting the input voltage signal, the duty ratio and resonant frequency of the control voltage signal, the present invention ensures an optimal power transmission efficiency of the wireless power transmission system. Moreover, parameters of a charge pump reservoir and gate driving circuit can be further designed in view of the trend feedback of its gate drive waveforms so as to optimize the effect of the proposed invention.Type: ApplicationFiled: May 28, 2021Publication date: September 8, 2022Applicant: National Yang Ming Chiao Tung UniversityInventors: Wei-Hua Chieng, Edward Yi Chang, Stone Cheng, Shyr-Long Jeng, Newton Tang, Chih-Chiang Wu, Ching-Yao Liu, Kuo-Bin Wang
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Publication number: 20220223710Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.Type: ApplicationFiled: March 30, 2022Publication date: July 14, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yi-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
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Patent number: 11387824Abstract: A voltage-controlled varied frequency pulse width modulator is provided, including a frequency-regulating voltage output device which receives a determining voltage, decides a resonant frequency according to the determining voltage and outputs an oscillation signal having the resonant frequency. A duty-ratio-regulating voltage output device receives the oscillation signal and a reference signal to determine a duty ratio through an inverting closed loop, so as to adjust the oscillation signal to have the duty ratio. By employing the proposed voltage-controlled modulator circuit with tunable frequency and varied pulse width of the present invention, a modulation signal having the determined resonant frequency and duty ratio is obtained. Moreover, the present invention can be further combined with gate drive waveform trend feedback designs to achieve superior power transmission efficiency of a wireless power transmission system to optimize the inventive effect of the present invention.Type: GrantFiled: October 29, 2021Date of Patent: July 12, 2022Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Wei-Hua Chieng, Edward Yi Chang, Stone Cheng, Shyr-Long Jeng, Li-Chuan Tang, Chih-Chiang Wu, Yueh-Tsung Hsieh, Ching-Yao Liu, Kuo-Bin Wang
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Publication number: 20220209694Abstract: An operation method and an operation device of a motor driver for driving a motor are provided. The operation method includes: establishing a hysteresis control method; and adjusting a switch frequency of a power module for operating the motor by using the hysteresis control method according to a change of rotation speed of the motor and a current switch frequency.Type: ApplicationFiled: December 29, 2020Publication date: June 30, 2022Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chih-Chiang WU, Yun-Huan LI, Hsin-Ping CHOU, Shih-Hsiang WU
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Patent number: 11374515Abstract: An operation method and an operation device of a motor driver for driving a motor are provided. The operation method includes: establishing a hysteresis control method; and adjusting a switch frequency of a power module for operating the motor by using the hysteresis control method according to a change of rotation speed of the motor and a current switch frequency.Type: GrantFiled: December 29, 2020Date of Patent: June 28, 2022Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chih-Chiang Wu, Yun-Huan Li, Hsin-Ping Chou, Shih-Hsiang Wu
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Publication number: 20220140080Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.Type: ApplicationFiled: January 20, 2022Publication date: May 5, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shi-You Liu, Tsai-Yu Wen, Ching-I Li, Ya-Yin Hsiao, Chih-Chiang Wu, Yu-Chun Liu, Ti-Bin Chen, Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu
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Patent number: 11322598Abstract: A semiconductor device includes a substrate having a first region and a second region and a gate structure on the first region and the second region of the substrate. The gate structure includes a first bottom barrier metal (BBM) layer on the first region and the second region, a first work function metal (WFM) layer on the first region; and a diffusion barrier layer on a top surface and a sidewall of the first WFM layer on the first region and the first BBM layer on the second region. Preferably, a thickness of the first BBM layer on the second region is less than a thickness of the first BBM layer on the first region.Type: GrantFiled: June 21, 2020Date of Patent: May 3, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: YI-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
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Patent number: 11271078Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.Type: GrantFiled: April 1, 2020Date of Patent: March 8, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shi-You Liu, Tsai-Yu Wen, Ching-I Li, Ya-Yin Hsiao, Chih-Chiang Wu, Yu-Chun Liu, Ti-Bin Chen, Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu
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Patent number: 11062926Abstract: Apparatus and method for monitoring wafer charges are proposed. A conductive pin, a conductive spring and a conductive line are configured in series to connect the backside surface of the wafer and the sample conductor so that the backside surface of the wafer and the surface of the sample conductor have identical charge density. Hence, by using a static electricity sensor positioned close to the surface of the sample conductor, the charges on the wafer may be monitored. Note that the charges appeared on the frontside surface of the wafer induces charges on the backside surface of the wafer. The sample conductor is a sheet conductor and properly insulated from the surrounding environment. As usual, the sample conductor and the static electricity sensor are positioned outside the chamber where the wafer is placed and processed, so as to simplify the apparatus inside the chamber and reduce the contamination risk.Type: GrantFiled: October 4, 2019Date of Patent: July 13, 2021Assignee: ADVANCED ION BEAM TECHNOLOGY, INC.Inventors: Chih-Chiang Wu, Chun-Chin Kang, Yu-Ho Ni, Chien-Ta Feng
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Publication number: 20210202439Abstract: A high power module is provided, which includes a substrate, plural first power chips, plural second power chips, a positive electrode plate and a negative electrode plat. The substrate includes a first metal area, a second metal area, a third metal area disposed between the first metal area and the second metal area. The first power chips are disposed on the third metal area and connected to the first metal area via plural first connection elements. The second power chips are disposed on the second metal area and connected to the third metal area via plural second connection elements. The positive electrode plate is C-shaped and connected to the first metal area. The negative electrode plate is C-shaped and connected to the second metal area; the direction of the opening of the negative electrode plate is contrary to that of the opening of the positive electrode plate.Type: ApplicationFiled: December 26, 2019Publication date: July 1, 2021Inventors: CHIH-CHIANG WU, MING-TSAN PENG, SHIH-KAI HSIEH, LI-SONG LIN, CHENG-HAN HO, YEU-JOU LIN
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Publication number: 20210202344Abstract: A semiconductor device includes an insulating thermal substrate, a metal wiring layer and a heat-dissipation component. The metal wiring layer includes a plurality of engaging structures. The plurality of engaging structures is disposed between the insulating thermal substrate and the heat-dissipation component, and the heat-dissipation component applies solder structures to connect the metal wiring layer by having the solder structures to wrap partly the plurality of engaging structures. In addition, a method for fabricating the same semiconductor device is also provided.Type: ApplicationFiled: December 26, 2019Publication date: July 1, 2021Inventors: CHIH-CHIANG WU, CHENG-HAN HO, SHIH-KAI HSIEH, LI-SONG LIN
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Publication number: 20200321442Abstract: A semiconductor device includes a substrate having a first region and a second region and a gate structure on the first region and the second region of the substrate. The gate structure includes a first bottom barrier metal (BBM) layer on the first region and the second region, a first work function metal (WFM) layer on the first region; and a diffusion barrier layer on a top surface and a sidewall of the first WFM layer on the first region and the first BBM layer on the second region. Preferably, a thickness of the first BBM layer on the second region is less than a thickness of the first BBM layer on the first region.Type: ApplicationFiled: June 21, 2020Publication date: October 8, 2020Inventors: Yi-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
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Patent number: 10734496Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first bottom barrier metal (BBM) layer on the first region and the second region; forming a first work function metal layer on the first BBM layer on the first region and the second region; removing the first work function metal (WFM) layer and part of the first BBM layer on the second region; and forming a diffusion barrier layer on the first WFM layer on the first region and the first BBM layer on the second region.Type: GrantFiled: October 31, 2018Date of Patent: August 4, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
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Publication number: 20200235208Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.Type: ApplicationFiled: April 1, 2020Publication date: July 23, 2020Inventors: Shi-You Liu, Tsai-Yu Wen, Ching-I Li, Ya-Yin Hsiao, Chih-Chiang Wu, Yu-Chun Liu, Ti-Bin Chen, Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu