Patents by Inventor Chih-Chieh Yeh

Chih-Chieh Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Accumulation type FinFET, circuits and fabrication method thereof
    Patent number: 8264032
    Abstract: A FinFET includes a substrate and a fin structure on the substrate. The fin structure includes a channel between a source and a drain, wherein the source, the drain, and the channel have the first type dopant. The channel includes a Ge, SiGe, or III-V semiconductor. A gate dielectric layer is located over the channel and a gate is located over the gate dielectric layer.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: September 11, 2012
    Inventors: Chih Chieh Yeh, Chih-Sheng Chang, Clement Hsingjen Wann
  • Finfets and methods for forming the same
    Patent number: 8264021
    Abstract: A Fin field effect transistor (FinFET) includes a fin-channel body over a substrate. A gate electrode is disposed over the fin-channel body. At least one source/drain (S/D) region is disposed adjacent to the fin-channel body. The at least one S/D region is substantially free from including any fin structure.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: September 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Shyue Lai, Tsz-Mei Kwok, Chih Chieh Yeh, Clement Hsingjen Wann
  • Systems and methods for programming a memory device
    Patent number: 8223553
    Abstract: A multi-Level Cell (MLC) can be used to store, for example, 4 bits per cell by storing two bits on each of two sides. Each side can store, e.g., four different current level states that can be determined by the number of holes injected into, e.g., nitride layer, during programming. As more holes are injected the current decreases for a given voltage. The current can be low, therefore, it can be advantageous in one embodiment to use a current amplifier. The current amplifier can be a BJT, MOS or other type of device.
    Type: Grant
    Filed: October 12, 2005
    Date of Patent: July 17, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih Chieh Yeh, Wen Jer Tsai, Yi Ying Liao
  • FIN-LIKE FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD OF MANUFACTURING SAME
    Publication number: 20120012932
    Abstract: A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a semiconductor substrate; a fin structure disposed over the semiconductor substrate; and a gate structure disposed on a portion of the fin structure. The gate structure traverses the fin structure and separates a source region and a drain region of the fin structure, the source and drain region defining a channel therebetween. The source and drain region of the fin structure include a strained source and drain feature. The strained source feature and the strained drain feature each include: a first portion having a first width and a first depth; and a second portion disposed below the first portion, the second portion having a second width and a second depth. The first width is greater than the second width, and the first depth is less than the second depth.
    Type: Application
    Filed: July 15, 2010
    Publication date: January 19, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsu-Hsiu Perng, Chih Chieh Yeh, Tzu-Chiang Chen, Chia-Cheng Ho, Chih-Sheng Chang
  • FinFETs with Multiple Fin Heights
    Publication number: 20110133292
    Abstract: An integrated circuit structure includes a semiconductor substrate, and a FinFET over the semiconductor substrate. The FinFET includes a semiconductor fin; a gate dielectric on a top surface and sidewalls of the semiconductor fin; a gate electrode on the gate dielectric; and a source/drain region at an end of the semiconductor fin. A first pair of shallow trench isolation (STI) regions includes portions directly underlying portions of the source/drain regions, wherein the first pair of STI regions is separated by, and adjoining a semiconductor strip. The first pair of STI regions further has first top surfaces. A second pair of STI regions comprises portions directly underlying the gate electrode, wherein the second pair of STI regions is separated from each other by, and adjoining, the semiconductor strip. The second pair of STI regions has second top surfaces higher than the first top surfaces.
    Type: Application
    Filed: July 26, 2010
    Publication date: June 9, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Chang-Yun Chang, Feng Yuan
  • SACRIFICIAL OFFSET PROTECTION FILM FOR A FINFET DEVICE
    Publication number: 20110117679
    Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary embodiment of the method includes providing a substrate; forming a fin structure over the substrate; forming a gate structure, wherein the gate structure overlies a portion of the fin structure; forming a sacrificial-offset-protection layer over another portion of the fin structure; and thereafter performing an implantation process.
    Type: Application
    Filed: November 19, 2009
    Publication date: May 19, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Lin Lee, Feng Yuan, Chih Chieh Yeh
  • FinFET Design with Reduced Current Crowding
    Publication number: 20110095378
    Abstract: An integrated circuit structure includes a substrate and a fin field-effect transistor (FinFET). The FinFET includes a fin over the substrate and having a first fin portion and a second fin portion. A gate stack is formed on a top surface and sidewalls of the first fin portion. An epitaxial semiconductor layer has a first portion formed directly over the second fin portion, and a second portion formed on sidewalls of the second fin portion. A silicide layer is formed on the epitaxial semiconductor layer. A peripheral ratio of a total length of an effective silicide peripheral of the FinFET to a total length of a fin peripheral of the FinFET is greater than 1.
    Type: Application
    Filed: July 23, 2010
    Publication date: April 28, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh
  • FINFETS AND METHODS FOR FORMING THE SAME
    Publication number: 20110079829
    Abstract: A Fin field effect transistor (FinFET) includes a fin-channel body over a substrate. A gate electrode is disposed over the fin-channel body. At least one source/drain (S/D) region is disposed adjacent to the fin-channel body. The at least one S/D region is substantially free from including any fin structure.
    Type: Application
    Filed: April 16, 2010
    Publication date: April 7, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Shyue LAI, Tsz-Mei KWOK, Chih Chieh YEH, Clement Hsingjen WANN
  • Germanium FinFETs with Metal Gates and Stressors
    Publication number: 20110068407
    Abstract: An integrated circuit structure includes an n-type fin field effect transistor (FinFET) and a p-type FinFET. The n-type FinFET includes a first germanium fin over a substrate; a first gate dielectric on a top surface and sidewalls of the first germanium fin; and a first gate electrode on the first gate dielectric. The p-type FinFET includes a second germanium fin over the substrate; a second gate dielectric on a top surface and sidewalls of the second germanium fin; and a second gate electrode on the second gate dielectric. The first gate electrode and the second gate electrode are formed of a same material having a work function close to an intrinsic energy level of germanium.
    Type: Application
    Filed: July 7, 2010
    Publication date: March 24, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih Chieh Yeh, Chih-Sheng Chang, Clement Hsingjen Wann
  • ACCUMULATION TYPE FINFET, CIRCUITS AND FABRICATION METHOD THEREOF
    Publication number: 20110049613
    Abstract: A FinFET includes a substrate and a fin structure on the substrate. The fin structure includes a channel between a source and a drain, wherein the source, the drain, and the channel have the first type dopant. The channel includes a Ge, SiGe, or III-V semiconductor. A gate dielectric layer is located over the channel and a gate is located over the gate dielectric layer.
    Type: Application
    Filed: April 9, 2010
    Publication date: March 3, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Chieh YEH, Chih-Sheng CHANG, Clement Hsingjen WANN
  • Gated diode nonvolatile memory process
    Patent number: 7888707
    Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: February 15, 2011
    Assignee: Macronix International Co., Ltd.
    Inventors: Yi Ying Liao, Wen Jer Tsai, Chih Chieh Yeh
  • METHOD FOR FORMING HIGH GERMANIUM CONCENTRATION SIGE STRESSOR
    Publication number: 20110024804
    Abstract: A method for producing a SiGe stressor with high Ge concentration is provided. The method includes providing a semiconductor substrate with a source area, a drain area, and a channel in between; depositing the first SiGe film layer on the source area and/or the drain area; performing a low temperature thermal oxidation, e.g., a high water vapor pressure wet oxidation, to form an oxide layer at the top of the first SiGe layer and to form the second SiGe film layer with high Ge percentage at the bottom of the first SiGe film layer without Ge diffusion into the semiconductor substrate; performing a thermal diffusion to form the SiGe stressor from the second SiGe film layer, wherein the SiGe stressor provides uniaxial compressive strain on the channel; and removing the oxide layer. A Si cap layer can be deposited on the first SiGe film layer prior to performing oxidation.
    Type: Application
    Filed: July 7, 2010
    Publication date: February 3, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Hao CHANG, Jeff J. XU, Chien-Hsun WANG, Chih Chieh YEH, Chih-Hsiang CHANG
  • Recessed shallow trench isolation
    Patent number: 7804152
    Abstract: In some embodiments, a memory integrated circuit has different shallow trench isolation structures in the memory circuitry of the memory integrated circuit and the control circuitry of the memory integrated circuit. The isolation dielectric fills the trenches of the shallow trench isolation structures to different degrees. In some embodiments, a memory integrated circuit has memory circuitry with shallow trench isolation structures and intermediate regions. The memory circuitry supports a channel between neighboring nonvolatile memory devices supporting multiple current components with different orientations. In some embodiments, recessed shallow trench isolation structures are formed.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: September 28, 2010
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih Chieh Yeh, Wen Jer Tsai
  • NAND type multi-bit charge storage memory array and methods for operating and fabricating the same
    Patent number: 7710774
    Abstract: A NAND type multi-bit charge storage memory array comprises a first and a second memory strings each of which includes one or more charge storage memory cells and two select transistors. The charge storage memory cells are connected in series to form a memory cell string. The two select transistors are connected in series to both ends of the memory cell string, respectively. The NAND type multi-bit charge storage memory array further comprises a shared bit line and a first and a second bit lines. The shared bit line is connected with the first ends of the first and the second memory strings. The first and the second bit lines are connected to the second ends of the first and the second memory strings, respectively. The first select transistor and the second select transistor of each memory string are controlled by a first and a second select transistor control lines, respectively.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: May 4, 2010
    Assignee: Macronix International Co., Ltd.
    Inventors: Yin Jen Chen, Chun Lein Su, Ming Shiang Chin, Chih Chieh Yeh, Tzung Ting Han
  • METAL GATE STRESS FILM FOR MOBILITY ENHANCEMENT IN FinFET DEVICE
    Publication number: 20100072553
    Abstract: A CMOS FinFET semiconductor device provides an NMOS FinFET device that includes a compressive stress metal gate layer over semiconductor fins and a PMOS FinFET device that includes a tensile stress metal gate layer over semiconductor fins. A process for forming the same includes a selective annealing process that selectively converts a compressive metal gate film formed over the PMOS device to the tensile stress metal gate film.
    Type: Application
    Filed: September 23, 2008
    Publication date: March 25, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jeff J. XU, Clement H. Wann, Chih Chieh Yeh, Chih-Sheng Chang
  • Gated diode nonvolatile memory cell array
    Patent number: 7672157
    Abstract: A memory integrated circuit has memory arrays that are vertically layered. These memory arrays include word lines and bit lines. Intersections between the word lines and the bit lines include a diode and a memory state storage element. The diode and the memory storage element are connected in between a word line and a bit line. The diode at the intersections includes a first diode node and a second diode node. Various aspects of the memory integrated circuit are electrically interconnected in various ways, such as corresponding word lines, corresponding first diode nodes, or corresponding second diode nodes of different memory arrays being electrically interconnected. Various aspects of the memory integrated circuit are isolated in various ways, such as word lines, first diode nodes, or second diode nodes of different memory arrays being isolated.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: March 2, 2010
    Assignee: Macronix International Co., Ltd.
    Inventors: Yi Ying Liao, Wen Jer Tsai, Chih Chieh Yeh
  • Recessed Shallow Trench Isolation
    Publication number: 20090155978
    Abstract: In some embodiments, a memory integrated circuit has different shallow trench isolation structures in the memory circuitry of the memory integrated circuit and the control circuitry of the memory integrated circuit. The isolation dielectric fills the trenches of the shallow trench isolation structures to different degrees. In some embodiments, a memory integrated circuit has memory circuitry with shallow trench isolation structures and intermediate regions. The memory circuitry supports a channel between neighboring nonvolatile memory devices supporting multiple current components with different orientations. In some embodiments, recessed shallow trench isolation structures are formed.
    Type: Application
    Filed: February 25, 2009
    Publication date: June 18, 2009
    Applicant: Macronix International Co., Ltd.
    Inventors: Chih Chieh Yeh, Wen Jer Tsai
  • Integrated code and data flash memory
    Patent number: 7529128
    Abstract: A memory architecture for an integrated circuit comprises a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another pattern of data usage. The first and second memory arrays comprise charge storage based nonvolatile memory cells having substantially the same structure in both arrays. A first operation algorithm adapted for example for data flash applications is used for programming, erasing and reading data in the first memory array. A second operation algorithm adapted for example for code flash applications is used for programming, erasing and reading data in the second memory array, wherein the second operation algorithm is different than the first operation algorithm. Thus, one die with memory for both code flash and data flash applications can be easily manufactured using a simple process, at low cost and high yield.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: May 5, 2009
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih Chieh Yeh, Wen Jer Tsai, Tao Cheng Lu, Chih Yuan Lu
  • Recessed shallow trench isolation
    Patent number: 7514742
    Abstract: In some embodiments, a memory integrated circuit has different shallow trench isolation structures in the memory circuitry of the memory integrated circuit and the control circuitry of the memory integrated circuit. The isolation dielectric fills the trenches of the shallow trench isolation structures to different degrees. In some embodiments, a memory integrated circuit has memory circuitry with shallow trench isolation structures and intermediate regions. The memory circuitry supports a channel between neighboring nonvolatile memory devices supporting multiple current components with different orientations. In some embodiments, recessed shallow trench isolation structures are formed.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: April 7, 2009
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih Chieh Yeh, Wen Jer Tsai
  • Gated Diode Nonvolatile Memory Cell Array
    Publication number: 20090080254
    Abstract: A memory integrated circuit has memory arrays that are vertically layered. These memory arrays include word lines and bit lines. Intersections between the word lines and the bit lines include a diode and a memory state storage element. The diode and the memory storage element are connected in between a word line and a bit line. The diode at the intersections includes a first diode node and a second diode node. Various aspects of the memory integrated circuit are electrically interconnected in various ways, such as corresponding word lines, corresponding first diode nodes, or corresponding second diode nodes of different memory arrays being electrically interconnected. Various aspects of the memory integrated circuit are isolated in various ways, such as word lines, first diode nodes, or second diode nodes of different memory arrays being isolated.
    Type: Application
    Filed: December 2, 2008
    Publication date: March 26, 2009
    Applicant: Macronix International Co., Ltd.
    Inventors: Yi Ying Liao, Wen Jer Tsai, Chih Chieh Yeh