Abstract: An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions. The structure further includes a second semiconductor strip, wherein the first and the second semiconductor strips are formed of the same semiconductor material. Second isolation regions are on opposite sides of the second semiconductor strip. A second epitaxy strip overlaps the second semiconductor strip. A top portion of the second epitaxy strip is over a second top surface of the second isolation regions. The first epitaxy strip and the second epitaxy strip are formed of different semiconductor materials. A bottom surface of the first epitaxy strip is lower than a bottom surface of the second epitaxy strip.

Abstract: An embodiment is an integrated circuit structure including two insulation regions over a substrate with one of the two insulation regions including a void, at least a bottom surface of the void being defined by the one of the two insulation regions. The integrated circuit structure further includes a first semiconductor strip between and adjoining the two insulation regions, where the first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions, a gate dielectric over a top surface and sidewalls of the fin, and a gate electrode over the gate dielectric.

Abstract: An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions. The structure further includes a second semiconductor strip, wherein the first and the second semiconductor strips are formed of the same semiconductor material. Second isolation regions are on opposite sides of the second semiconductor strip. A second epitaxy strip overlaps the second semiconductor strip. A top portion of the second epitaxy strip is over a second top surface of the second isolation regions. The first epitaxy strip and the second epitaxy strip are formed of different semiconductor materials. A bottom surface of the first epitaxy strip is lower than a bottom surface of the second epitaxy strip.

Abstract: An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.

Abstract: A method of fabricating a semiconductor device includes providing a substrate having a fin disposed thereon. A gate structure is formed on the fin. The gate structure interfaces at least two sides of the fin. A stress film is formed on the substrate including on the fin. The substrate including the stress film is annealed. The annealing provides a tensile strain in a channel region of the fin. For example, a compressive strain in the stress film may be transferred to form a tensile stress in the channel region of the fin.

Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.

Abstract: A device including a substrate having a fin. A metal gate structure is formed on the fin. The metal gate structure includes a stress metal layer formed on the fin such that the stress metal layer extends to a first height from an STI feature, the first height being greater than the fin height. A conduction metal layer is formed on the stress metal layer.

Abstract: An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.

Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.

Abstract: A semiconductor device and method of fabricating thereof is described that includes a substrate having a fin with a top surface and a first and second lateral sidewall. A hard mask layer may be formed on the top surface of the fin (e.g., providing a dual-gate device). A gate dielectric layer and work function metal layer are formed on the first and second lateral sidewalls of the fin. A silicide layer is formed on the work function metal layer on the first and the second lateral sidewalls of the fin. The silicide layer may be a fully-silicided layer and may provide a stress to the channel region of the device disposed in the fin.

Abstract: A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a semiconductor substrate; a fin structure disposed over the semiconductor substrate; and a gate structure disposed over a portion of the fin structure. The gate structure traverses the fin structure and separates a source region and a drain region of the fin structure, the source and drain region defining a channel therebetween. The source and drain region of the fin structure include a strained source and drain feature. The strained source feature and the strained drain feature each include: a first portion having a first width and a first depth; and a second portion disposed below the first portion, the second portion having a second width and a second depth. The first width is greater than the second width, and the first depth is less than the second depth.

Abstract: An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.

Abstract: A method and device including a substrate having a fin. A metal gate structure is formed on the fin. The metal gate structure includes a stress metal layer formed on the fin such that the stress metal layer extends to a first height from an STI feature, the first height being greater than the fin height. A conduction metal layer is formed on the stress metal layer.

Abstract: This description relates to a fin field-effect-transistor (FinFET) including a substrate and a fin structure on the substrate. The fin structure includes a channel between a source and a drain, wherein the source, the drain, and the channel have a first type dopant, and the channel comprises at least one of a Ge, SiGe, or III-V semiconductor. The FinFET further includes a gate dielectric layer over the channel and a gate over the gate dielectric layer. The FinFET further includes a nitride spacer on the substrate adjacent the gate and an oxide layer between the nitride spacer and the gate and between the nitride spacer and the substrate.

Abstract: A semiconductor device and method of fabricating thereof is described that includes a substrate having a fin with a top surface and a first and second lateral sidewall. A hard mask layer may be formed on the top surface of the fin (e.g., providing a dual-gate device). A gate dielectric layer and work function metal layer are formed on the first and second lateral sidewalls of the fin. A silicide layer is formed on the work function metal layer on the first and the second lateral sidewalls of the fin. The silicide layer may be a fully-silicided layer and may provide a stress to the channel region of the device disposed in the fin.

Abstract: An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions. The structure further includes a second semiconductor strip, wherein the first and the second semiconductor strips are formed of the same semiconductor material. Second isolation regions are on opposite sides of the second semiconductor strip. A second epitaxy strip overlaps the second semiconductor strip. A top portion of the second epitaxy strip is over a second top surface of the second isolation regions. The first epitaxy strip and the second epitaxy strip are formed of different semiconductor materials. A bottom surface of the first epitaxy strip is lower than a bottom surface of the second epitaxy strip.

Abstract: An embodiment is an integrated circuit structure including two insulation regions over a substrate with one of the two insulation regions including a void, at least a bottom surface of the void being defined by the one of the two insulation regions. The integrated circuit structure further includes a first semiconductor strip between and adjoining the two insulation regions, where the first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions, a gate dielectric over a top surface and sidewalls of the fin, and a gate electrode over the gate dielectric.

Abstract: A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a semiconductor substrate; a fin structure disposed over the semiconductor substrate; and a gate structure disposed on a portion of the fin structure. The gate structure traverses the fin structure and separates a source region and a drain region of the fin structure, the source and drain region defining a channel therebetween. The source and drain region of the fin structure include a strained source and drain feature. The strained source feature and the strained drain feature each include: a first portion having a first width and a first depth; and a second portion disposed below the first portion, the second portion having a second width and a second depth. The first width is greater than the second width, and the first depth is less than the second depth.

Abstract: An integrated circuit structure includes a semiconductor substrate, and a FinFET over the semiconductor substrate. The FinFET includes a semiconductor fin; a gate dielectric on a top surface and sidewalls of the semiconductor fin; a gate electrode on the gate dielectric; and a source/drain region at an end of the semiconductor fin. A first pair of shallow trench isolation (STI) regions includes portions directly underlying portions of the source/drain regions, wherein the first pair of STI regions is separated by, and adjoining a semiconductor strip. The first pair of STI regions further has first top surfaces. A second pair of STI regions comprises portions directly underlying the gate electrode, wherein the second pair of STI regions is separated from each other by, and adjoining, the semiconductor strip. The second pair of STI regions has second top surfaces higher than the first top surfaces.

Abstract: An integrated circuit transistor structure includes a semiconductor substrate, a first SiGe layer in at least one of a source area or a drain area on the semiconductor substrate, and a channel between the source area and the drain area. The first SiGe layer has a Ge concentration of 50 percent or more.