Abstract: Charge trapping memory cells are protected from over-erasing in response to an erase command. For example, in response to an erase command, one bias arrangement is applied to program charge trapping memory cells, and another bias arrangement is applied to erase the charge trapping memory cells, such that the charge trapping memory cells have a higher net electron charge, in the erased state than i.n the programmed state. In another example, an integrated circuit with an array of charge trapping memory cells has logic which responds to an erase command by applying similar bias arrangements to the charge trapping memory cells. In a further example, such an integrated circuit is manufactured.

Abstract: A method for manufacturing a multiple-gate memory cell which comprises a semiconductor body and a plurality of gates arranged in series and the semiconductor body includes first forming a plurality of gates spaced apart by about a gate width, forming an isolation layer on the sidewalls, and filling between the first plurality of gates to form a second plurality of gates. A charge storage structure is formed on the semiconductor body beneath each of all or some of the gates in the plurality of gates. Circuitry is formed to conduct source and drain bias voltages to the semiconductor body near a first gate and a last gate in the series, and circuitry to conduct gate bias voltages to the plurality of gates is included. The multiple-gate memory cell includes a continuous, multiple-gate channel region beneath the plurality of gates in the series, with charge storage locations between some or all of the gates.

Abstract: A memory cell with a charge trapping structure is read by measuring current between the substrate region of the memory cell and one of the source region of the memory cell and the drain region of the memory cell. The read operation decreases the coupling between different parts of the charge trapping structure when other parts of the charge trapping structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: An architecture, circuit and method for providing a very dense, producible, non volatile FLASH memory with SONOS cells. Preferred SONOS memory cells are formed using a uniformly doped channel region. A FinFET embodiment and a planar FD-SOI embodiment cell are disclosed. Because the novel SONOS cells do not rely on diffused regions, the cells may be formed into a three dimensional array of cells without diffusion problems from subsequent thermal processing steps. FLASH memory arrays are formed by forming layers of NAND Flash cells in the local interconnect layers of an integrated circuit, with the metal layers forming the global bit line conductors. The three dimensional non volatile arrays formed of the SONOS cells rely on conventional semiconductor processing and so are easily integrated with other circuitry to form an ASIC or SoC device. P-channel and n-channel devices may be used to form the SONOS non-volatile cells.

Abstract: A method of reducing gate disturb in a charge-trapping layer memory cell by applying different Vpass voltages to different sides of a selected wordline. A higher Vpass voltage is used to pass higher source/drain voltage and a lower Vpass voltage is used to pass a lower source/drain voltage. By controlling the Vpass voltages on different sides of a selected wordline, it is possible to reduce a vertical field that is established in a gate region when the Vpass voltages are applied. A reduced vertical field results in suppressed gate disturb. The method also includes a novel bit-line biasing scheme that may further reduce the vertical field and thereby may further suppress gate disturb, particularly in an array of memory cells.

Abstract: Methods and apparatuses for causing electroluminescence with charge trapping structures are disclosed. Various embodiments relate to methods and apparatuses for causing electroluminescence with charge carriers of one type provided to the charge trapping structure by a forward biased p-n structure or a reverse biased p-n structure.

Abstract: A circuit of non-volatile memory which includes a plurality of memory units is disclosed. The memory unit comprises a first switch, a second switch, a data line, a voltage storage component, and a plurality of memory components connected in series. The first terminal of the first switch is coupled to the first voltage. The data line is coupled to the second terminal of the first switch. The first terminal of the voltage storage component is coupled to the data line, and the second terminal of the voltage storage component is coupled to the ground. The first terminal of the second switch is coupled the data line. In addition, the third terminal of each memory component is coupled to the first terminal of the next memory component, and the second terminal of the each memory component is coupled to second voltage.

Abstract: An array of charge trapping nonvolatile memory cells is arranged in several columns of cells, each arranged in a series, such as a NAND string. Each cell stores no more than a single charge storage state.

Abstract: A multi-Level Cell (MLC) can be used to store, for example, 4 bits per cell by storing two bits on each of two sides. Each side can store, e.g., four different current level states that can be determined by the number of holes injected into, e.g., nitride layer, during programming. As more holes are injected the current decreases for a given voltage. The current can be low, therefore, it can be advantageous in one embodiment to use a current amplifier. The current amplifier can be a BJT, MOS or other type of device.

Abstract: A method for manufacturing a multiple-gate memory cell which comprises a semiconductor body and a plurality of gates arranged in series and the semiconductor body includes first forming a plurality of gates spaced apart by about a gate width, forming an isolation layer on the sidewalls, and filling between the first plurality of gates to form a second plurality of gates. A charge storage structure is formed on the semiconductor body beneath each of all or some of the gates in the plurality of gates. Circuitry is formed to conduct source and drain bias voltages to the semiconductor body near a first gate and a last gate in the series, and circuitry to conduct gate bias voltages to the plurality of gates is included. The multiple-gate memory cell includes a continuous, multiple-gate channel region beneath the plurality of gates in the series, with charge storage locations between some or all of the gates.

Abstract: A memory cell with a charge trapping structure is read by measuring current between the substrate region of the memory cell and one of the source region of the memory cell and the drain region of the memory cell. The read operation decreases the coupling between different parts of the charge trapping structure when other parts of the charge trapping structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A string of memory cells with a charge trapping structure is read, by selecting part of a memory cell selected by a word line. Part of the memory cell is selected by turning on one of the pass transistors on either side of the string of memory cells. The charge storage state of the selected part is determined by measuring current in a bit line tied to both pass transistors.

Abstract: A memory cell with a charge trapping structure is read by measuring current between the substrate region of the memory cell and one of the source region of the memory cell and the drain region of the memory cell. The read operation decreases the coupling between different parts of the charge trapping structure when other parts of the charge trapping structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation.

Abstract: A memory cell with a charge trapping structure is operated by measuring current between the substrate region of the memory cell and at least one of the source region of the memory cell and the drain region of the memory cell. The read operation decreases the coupling between different parts of the charge trapping structure when other parts of the charge trapping structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. The memory cell is erased by increasing the net positive charge on the memory cell and programmed by increasing the net negative charge on the memory cell.

Abstract: A memory cell with a charge storage structure is read by measuring current between the substrate region of the memory cell and one of the current carrying nodes of the memory cell. The read operation decreases the coupling between different parts of the charge storage structure when other parts of the charge storage structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. Example arrangements are a series of memory cells, and an array of series of memory cells.

Abstract: A memory cell with a charge storage structure is read by measuring current between the substrate region of the memory cell and one of the current carrying nodes of the memory cell. The read operation decreases the coupling between different parts of the charge storage structure when other parts of the charge storage structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. Example arrangements are a series of memory cells, and an array of series of memory cells.

Abstract: A nonvolatile memory cell with a charge storage structure is read by measuring current (such as band-to-band current) between the substrate region of the memory cell and at least one of the current carrying nodes of the memory cell. To enhance the operation of the nonvolatile memory cell, the band structure engineering is used to alter the band structure between a bulk part of the device and another part of the device supporting the measurement current.

Abstract: A memory cell with a charge storage structure is read by measuring current between the substrate region of the memory cell and one of the current carrying nodes of the memory cell. The read operation decreases the coupling between different parts of the charge storage structure when other parts of the charge storage structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. Example arrangements are a single memory cell, a column or NOR-connected memory cells, and a virtual ground array of memory cells.