Abstract: A flash cell includes a gate and an erase gate. The gate is disposed on a substrate, wherein the gate includes a control gate on the substrate and a floating gate having a tip between the substrate and the control gate. The erase gate is disposed beside the gate, wherein the tip points toward the erase gate. The present invention also provides a flash cell forming process including the following steps. A gate is formed on a substrate, wherein the gate includes a floating gate on the substrate. An implantation process is performed on a side part of the floating gate, thereby forming a first doped region in the side part. At least a part of the first doped region is oxidized, thereby forming a floating gate having a tip.

Abstract: A flash cell includes a gate and an erase gate. The gate is disposed on a substrate, wherein the gate includes a control gate on the substrate and a floating gate having a tip between the substrate and the control gate. The erase gate is disposed beside the gate, wherein the tip points toward the erase gate. The present invention also provides a flash cell forming process including the following steps. A gate is formed on a substrate, wherein the gate includes a floating gate on the substrate. An implantation process is performed on a side part of the floating gate, thereby forming a first doped region in the side part. At least a part of the first doped region is oxidized, thereby forming a floating gate having a tip.

Abstract: A die stacking method is provided. The die stacking method includes executing a manufacturing recipe, and loading an interposer-die mapping file according to the manufacturing recipe. The interposer-die mapping file corresponds to an interposer wafer including interposer dies. The die stacking method also includes loading a combination setting data according to the interposer-die mapping file, and loading a top die number and a top-die ID code of a top-die mapping file according to the combination setting data and the interposer-die mapping file. The top-die ID code corresponds to a top wafer including top dies, and the top die number corresponds to one of the top dies. The die stacking method also includes disposing the one of the top dies of the top wafer on one of the interposer dies of the interposer wafer.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A plurality of select gates are formed on a memory region of a semiconductor substrate. Two charge storage structures are formed between two adjacent select gates. A source region is formed in the semiconductor substrate, and the source region is formed between the two adjacent select gates. An insulation block is formed between the two charge storage structures and formed on the source region. A memory gate is formed on the insulation block, and the memory gate is connected to the two charge storage structures.

Abstract: Embodiments of a die stacking apparatus are provided. The die stacking apparatus includes a storage device configured to contain a top wafer and an interposer wafer. The top wafer has a number of top dies, and the interposer wafer has a number of interposer dies. The die stacking apparatus also includes a carrier device configured to carry the interposer wafer, and a transferring device configured to transfer the interposer wafer to the carrier device and to dispose the top dies on the interposer dies. The die stacking apparatus further includes a process module configured to control the transferring device. The process module controls the transferring device to transfer the interposer wafer to the carrier device, and controls the transferring device to dispose the top dies on the interposer dies of the interposer wafer, which is stacked on the carrier device.

Abstract: A method for fabricating non-volatile memory device is disclosed. The method includes the steps of: providing a substrate having a stack structure thereon; performing a first oxidation process to form a first oxide layer on the substrate and the stack structure; etching the first oxide layer for forming a first spacer adjacent to the stack structure; performing a second oxidation process to form a second oxide layer on the substrate; forming a dielectric layer on the first spacer and the second oxide layer; and etching the dielectric layer for forming a second spacer.

Abstract: A non-volatile memory cell includes a substrate, an erase gate disposed on the substrate and having a top plane, two floating gates disposed respectively at both sides of the erase gate, two control gates disposed respectively on two floating gates, and two select gates disposed respectively at outer sides of the two floating gates, where the two select gates have tilted top planes which are symmetric to each other.

Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and extending down from the surface of the substrate, and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug penetrating into the isolation and reaching the bottom thereof; and a first doping electrode region having the second conductive type, formed within the second well and below the isolation to connect the conductive plug.

Abstract: A semiconductor device includes a semiconductor substrate, a buried layer disposed in the semiconductor substrate; a deep well disposed in the semiconductor substrate; a first doped region disposed in the deep well, wherein the first doped region contacts the buried layer; a conductive region having the first conductivity type surrounding and being adjacent to the first doped region, wherein the conductive region has a concentration higher than the first doped region; a first heavily doped region disposed in the first doped region; a well having a second conductivity type disposed in the deep well; a second heavily doped region disposed in the well; a gate disposed on the semiconductor substrate between the first heavily doped region and the second heavily doped region; and a first trench structure and a second trench structure, wherein a depth of the second trench structure is substantially deeper than a depth of the buried layer.

Abstract: The present invention provides a memory cell, which includes a substrate, a gate dielectric layer, a patterned material layer, a selection gate and a control gate. The gate dielectric layer is disposed on the substrate. The patterned material layer is disposed on the substrate, wherein the patterned material layer comprises a vertical portion and a horizontal portion. The selection gate is disposed on the gate dielectric layer and atone side of the vertical portion of the patterned material layer. The control gate is disposed on the horizontal portion of the patterned material layer and at another side of the vertical portion, wherein the vertical portion protrudes over a top of the selection gate. The present invention further provides another embodiment of a memory cell and manufacturing methods thereof.

Abstract: Embodiments of a die stacking apparatus are provided. The die stacking apparatus includes a storage device configured to contain a top wafer and an interposer wafer. The top wafer has a number of top dies, and the interposer wafer has a number of interposer dies. The die stacking apparatus also includes a carrier device configured to carry the interposer wafer, and a transferring device configured to transfer the interposer wafer to the carrier device and to dispose the top dies on the interposer dies. The die stacking apparatus further includes a process module configured to control the transferring device. The process module controls the transferring device to transfer the interposer wafer to the carrier device, and controls the transferring device to dispose the top dies on the interposer dies of the interposer wafer, which is stacked on the carrier device.

Abstract: A high voltage metal-oxide-semiconductor transistor device includes a substrate, at least an isolation structure formed in the substrate, a gate formed on the substrate, and a source region and a drain region formed in the substrate at respective sides of the gate. The isolation structure further includes a recess. The gate includes a first gate portion formed on a surface of the substrate and a second gate portion downwardly extending from the first gate portion and formed in the recess.

Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and extending down from the surface of the substrate, and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug penetrating into the isolation and reaching the bottom thereof; and a first doping electrode region having the second conductive type, formed within the second well and below the isolation to connect the conductive plug.

Abstract: A high voltage metal-oxide-semiconductor transistor device includes a substrate, at least an isolation structure formed in the substrate, a gate formed on the substrate, and a source region and a drain region formed in the substrate at respective sides of the gate. The isolation structure further includes a recess. The gate includes a first gate portion formed on a surface of the substrate and a second gate portion downwardly extending from the first gate portion and formed in the recess.

Abstract: A semiconductor device includes a semiconductor substrate, a buried layer disposed in the semiconductor substrate; a deep well disposed in the semiconductor substrate; a first doped region disposed in the deep well, wherein the first doped region contacts the buried layer; a conductive region having the first conductivity type surrounding and being adjacent to the first doped region, wherein the conductive region has a concentration higher than the first doped region; a first heavily doped region disposed in the first doped region; a well having a second conductivity type disposed in the deep well; a second heavily doped region disposed in the well; a gate disposed on the semiconductor substrate between the first heavily doped region and the second heavily doped region; and a first trench structure and a second trench structure, wherein a depth of the second trench structure is substantially deeper than a depth of the buried layer.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate comprising silicon, cleaning the substrate, performing a first low pressure chemical vapor deposition (LPCVD) process using a first source gas to selectively deposit a seeding layer of silicon (Si) over the substrate, performing a second LPCVD process using a second source gas to selectively deposit a first layer of silicon germanium (SiGe) over the layer of Si, the second source gas including hydrochloride at a first flow rate, and performing a third LPCVD process using a third source gas including hydrochloride at a second flow rate. The first flow rate is substantially lower than the second flow rate.

Abstract: A method of forming MOS devices is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode over the gate dielectric, forming a source/drain region in the semiconductor substrate, forming an additional layer, preferably by epitaxial growth, on the source/drain region, and siliciding at least a top portion of the additional layer. The additional layer compensates for at least a portion of the semiconductor material lost during manufacturing processes and increases the distance between the source/drain silicide and the substrate. As a result, the leakage current is reduced. A transistor formed using the preferred embodiment preferably includes a silicide over the gate electrode wherein the silicide extends beyond a sidewall boundary of the gate electrode.

Abstract: A focus adjustable method of an optical image is implemented by a numerical analysis. An external light beam is allowed to pass through a lens module, thereby generating an optical image. The focus values of the optical image at four corners thereof are computed according to specified formulas to obtain a two-dimensional geometric tilt vector T(X,Y), an image diagonal spinor D and an image tetragonal average value M. According to the values T(X,Y), D and M, the tilt amount and the tilt direction of the lens module are adjusted, the optical quality of the lens module is discriminated and the focus value distribution of the lens module is determined.

Abstract: MOS devices having localized stressors are provided. Embodiments of the invention comprise a gate electrode formed over a substrate and source/drain regions formed on either side of the gate electrode. The source/drain regions include an embedded stressor and a capping layer on the embedded stressor. Preferably, the embedded stressor has a lattice spacing greater than the substrate lattice spacing. In a preferred embodiment, the substrate is silicon and the embedded stressor is silicon germanium. A method of manufacturing is also provided, wherein strained PMOS and NMOS transistors may be formed simultaneously.

Abstract: A system and method for semiconductor CP (circuit probe) test management. A control request message is received from a client computer, directing alignment of a probe unit or a wafer in a prober, attachment of a probe pin of the probe unit on a specific area of the wafer, and subsequent execution of CP testing. At least one control command corresponding to the control request message is issued to direct the prober for alignment of the probe unit or the wafer, attachment of the probe pin of the probe unit on the specific area of the wafer, and subsequent execution of CP testing.