Patents by Inventor Chih-Chien Chang

Chih-Chien Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7587293
    Abstract: A system and method for semiconductor CP (circuit probe) test management. A control request message is received from a client computer, directing alignment of a probe unit or a wafer in a prober, attachment of a probe pin of the probe unit on a specific area of the wafer, and subsequent execution of CP testing. At least one control command corresponding to the control request message is issued to direct the prober for alignment of the probe unit or the wafer, attachment of the probe pin of the probe unit on the specific area of the wafer, and subsequent execution of CP testing.
    Type: Grant
    Filed: May 9, 2007
    Date of Patent: September 8, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chien Chang, Keng-Chia Yang, Yi-Sheng Huang, Ben Shin
  • Publication number: 20080281536
    Abstract: A system and method for semiconductor CP (circuit probe) test management. A control request message is received from a client computer, directing alignment of a probe unit or a wafer in a prober, attachment of a probe pin of the probe unit on a specific area of the wafer, and subsequent execution of CP testing. At least one control command corresponding to the control request message is issued to direct the prober for alignment of the probe unit or the wafer, attachment of the probe pin of the probe unit on the specific area of the wafer, and subsequent execution of CP testing.
    Type: Application
    Filed: May 9, 2007
    Publication date: November 13, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chien Chang, Keng-Chia Yang, Yi-Sheng Huang, Ben Shin
  • Publication number: 20070148919
    Abstract: A method for manufacturing a semiconductor device includes providing a substrate comprising silicon, cleaning the substrate, performing a first low pressure chemical vapor deposition (LPCVD) process using a first source gas to selectively deposit a seeding layer of silicon (Si) over the substrate, performing a second LPCVD process using a second source gas to selectively deposit a first layer of silicon germanium (SiGe) over the layer of Si, the second source gas including hydrochloride at a first flow rate, and performing a third LPCVD process using a third source gas including hydrochloride at a second flow rate. The first flow rate is substantially lower than the second flow rate.
    Type: Application
    Filed: December 22, 2005
    Publication date: June 28, 2007
    Inventors: Li-Te Lin, Pang-Yen Tsai, Chih-Chien Chang, Tze-Liang Lee
  • Publication number: 20070071349
    Abstract: A focus adjustable method of an optical image is implemented by a numerical analysis. An external light beam is allowed to pass through a lens module, thereby generating an optical image. The focus values of the optical image at four corners thereof are computed according to specified formulas to obtain a two-dimensional geometric tilt vector T(X,Y), an image diagonal spinor D and an image tetragonal average value M. According to the values T(X,Y), D and M, the tilt amount and the tilt direction of the lens module are adjusted, the optical quality of the lens module is discriminated and the focus value distribution of the lens module is determined.
    Type: Application
    Filed: November 10, 2005
    Publication date: March 29, 2007
    Inventors: Hou-Ching Chin, Chih-Chien Chang
  • Publication number: 20070057287
    Abstract: MOS devices having localized stressors are provided. Embodiments of the invention comprise a gate electrode formed over a substrate and source/drain regions formed on either side of the gate electrode. The source/drain regions include an embedded stressor and a capping layer on the embedded stressor. Preferably, the embedded stressor has a lattice spacing greater than the substrate lattice spacing. In a preferred embodiment, the substrate is silicon and the embedded stressor is silicon germanium. A method of manufacturing is also provided, wherein strained PMOS and NMOS transistors may be formed simultaneously.
    Type: Application
    Filed: September 15, 2005
    Publication date: March 15, 2007
    Inventors: Li-Te Lin, Chih-Chien Chang, Tze-Liang Lee
  • Publication number: 20070010051
    Abstract: A method of forming MOS devices is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode over the gate dielectric, forming a source/drain region in the semiconductor substrate, forming an additional layer, preferably by epitaxial growth, on the source/drain region, and siliciding at least a top portion of the additional layer. The additional layer compensates for at least a portion of the semiconductor material lost during manufacturing processes and increases the distance between the source/drain silicide and the substrate. As a result, the leakage current is reduced. A transistor formed using the preferred embodiment preferably includes a silicide over the gate electrode wherein the silicide extends beyond a sidewall boundary of the gate electrode.
    Type: Application
    Filed: July 5, 2005
    Publication date: January 11, 2007
    Inventors: Chii-Ming Wu, Chih-Wei Chang, Pang-Yen Tsai, Chih-Chien Chang
  • Patent number: 7142938
    Abstract: A manufacturing management system and method. The system includes a manufacturing execution system and a plurality of manufacturing sites coupled to the manufacturing execution system. The manufacturing execution system comprises management data to support the manufacturing sites. Each manufacturing site comprises a corresponding site attribute. At least one of the manufacturing sites receives a lot, queries the management data for the lot from the manufacturing execution system according to lot identification and the site attribute of the manufacturing site receiving the lot, and processes the lot accordingly.
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: November 28, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shiaw-Lin Chi, Kun-Chi Liu, Chien-Wei Wang, Chih-Chien Chang, Chang-Hsi Lin, Chien-Fei Cheng, Lieh-Jung Chen, Fang-Ni Wu, Birgie Kuo, Yi-Fang Su
  • Patent number: 7129184
    Abstract: A method of preparing a silicon layer or substrate surface for growing an epitaxial layer of SiGe thereon. The process comprises removing native oxide from the surface of the silicon with an HF solution, and then oxidizing the exposed silicon surface to form a chemically formed layer of silicon oxide of the process damaged silicon surface. The chemically formed layer of silicon oxide is then removed by a second HF cleaning process so as to leave a smooth silicon surface suitable for growing a SiGe layer.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: October 31, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Chang, Shun Wu Lin, Pang-Yen Tsai, Tze-Liang Lee, Shih-Chang Chen
  • Publication number: 20060228850
    Abstract: A method of reducing the pattern-loading effect for selective epitaxial growth. The method includes the steps of: forming a mask layer over a substrate; forming an isolation region in the substrate isolating an active region and a dummy active region; removing at least a portion of the mask layer in the active region and thus forming a first opening, the substrate being exposed through the first opening; removing at least a portion of the mask layer in the dummy active region and thus forming a second opening, the substrate being exposed through the second opening; and performing selective epitaxial growth simultaneously on the substrate in the first opening and second openings. By introducing the second opening wherein epitaxial growth occurs, the pattern density is more uniform and thus the pattern-loading effect is reduced.
    Type: Application
    Filed: April 6, 2005
    Publication date: October 12, 2006
    Inventors: Pang-Yen Tsai, Chih-Chien Chang, Indira Yang, Tze-Liang Lee, Shih-Chang Chen
  • Publication number: 20060113282
    Abstract: A method of preparing a silicon layer or substrate surface for growing an epitaxial layer of SiGe thereon. The process comprises removing native oxide from the surface of the silicon with an HF solution, and then oxidizing the exposed silicon surface to form a chemically formed layer of silicon oxide of the process damaged silicon surface. The chemically formed layer of silicon oxide is then removed by a second HF cleaning process so as to leave a smooth silicon surface suitable for growing a SiGe layer.
    Type: Application
    Filed: December 1, 2004
    Publication date: June 1, 2006
    Inventors: Chih-Chien Chang, Shun Lin, Pang-Yen Tsai, Tze-Liang Lee, Shih-Chang Chen
  • Publication number: 20060079978
    Abstract: A manufacturing management system and method. The system includes a manufacturing execution system and a plurality of manufacturing sites coupled to the manufacturing execution system. The manufacturing execution system comprises management data to support the manufacturing sites. Each manufacturing site comprises a corresponding site attribute. At least one of the manufacturing sites receives a lot, queries the management data for the lot from the manufacturing execution system according to lot identification and the site attribute of the manufacturing site receiving the lot, and processes the lot accordingly.
    Type: Application
    Filed: October 13, 2004
    Publication date: April 13, 2006
    Inventors: Shiaw-Lin Chi, Kun-Chi Liu, Chien-Wei Wang, Chih-Chien Chang, Chang-Hsi Lin, Chien-Fei Cheng, Lieh-Jung Chen, Fang-Ni Wu, Birgie Kuo, Yi-Fang Su
  • Publication number: 20060044266
    Abstract: The present invention discloses a motion testing method and system for testing optical sensing modules. A movable light source emitting a light beam projected onto photodetector arrays of the optical sensing modules. When the movable light source is moved under the control of a control signal, speckles formed in the light beam and detected by the photodetdectors will change accordingly. According to the changes of the speckles, moving signals are generated by control circuits of the optical sensing modules. A host computer thus compares each moving signal with the control signal, and determines a normal state when the movement pattern indicated by the moving signal is consistent with the control signal.
    Type: Application
    Filed: August 1, 2005
    Publication date: March 2, 2006
    Inventors: Hou-Ching Chin, Chih-Chien Chang
  • Publication number: 20050194987
    Abstract: A testing system for check-in control in wafer testing. The testing system comprises a testing tool, an optical character recognition (OCR) device, and a controller. The testing tool performs a testing process of an article. The OCR device reads optical characters disposed on the article. The controller, connected to the testing tool and the OCR device, automatically initiates a check-in process for the article according to the read optical characters.
    Type: Application
    Filed: March 4, 2004
    Publication date: September 8, 2005
    Inventors: Keng-Chia Yang, Chih-Chien Chang, Lieh-Jung Chen