Patents by Inventor Chih-Ching Wang
Chih-Ching Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8987824Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.Type: GrantFiled: November 22, 2011Date of Patent: March 24, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang, Wen-Hsing Hsieh, Tsung-Hsing Yu, Yi-Ming Sheu, Chih-Chieh Yeh, Ken-Ichi Goto, Zhiqiang Wu
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Publication number: 20150079752Abstract: System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.Type: ApplicationFiled: November 13, 2014Publication date: March 19, 2015Inventors: Zhiqiang Wu, Ken-Ichi Goto, Wen-Hsing Hsieh, Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang
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Patent number: 8981479Abstract: A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.Type: GrantFiled: December 17, 2013Date of Patent: March 17, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Ching Wang, Jon-Hsu Ho, Ching-Fang Huang, Wen-Hsing Hsieh, Tsung-Hsing Yu, Yi-Ming Sheu, Ken-Ichi Goto, Zhiqiang Wu
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Publication number: 20150044847Abstract: A method of forming an integrated circuit comprises forming a first doped region in a substrate using a first angle ion implantation performed on a first side of a gate structure. The gate structure has a length in a first direction and a width in a second direction. The method also comprises forming a second doped region in the substrate using a second angle ion implantation performed on a second side of the gate structure. The first angle ion implantation has a first implantation angle with respect to the second direction and the second angle ion implantation has a second implantation angle with respect to the second direction. Each of the first implantation angle and the second implantation angle is substantially larger than 0° and less than 90°.Type: ApplicationFiled: September 18, 2014Publication date: February 12, 2015Inventors: Zhiqiang WU, Yi-Ming SHEU, Tsung-Hsing YU, Kuan-Lun CHENG, Chih-Pin TSAO, Wen-Yuan CHEN, Chun-Fu CHENG, Chih-Ching WANG
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Patent number: 8890207Abstract: System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.Type: GrantFiled: December 22, 2011Date of Patent: November 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zhiqiang Wu, Ken-Ichi Goto, Wen-Hsing Hsieh, Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang
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Patent number: 8859380Abstract: A method of forming an integrated circuit includes forming a plurality of gate structures longitudinally arranged along a first direction over a substrate. A plurality of angle ion implantations are performed to the substrate. Each of the angle ion implantations has a respective implantation angle with respect to a second direction. The second direction is substantially parallel with a surface of the substrate and substantially orthogonal to the first direction. Each of the implantation angles is substantially larger than 0°.Type: GrantFiled: November 11, 2010Date of Patent: October 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zhiqiang Wu, Yi-Ming Sheu, Tsung-Hsing Yu, Kuan-Lun Cheng, Chih-Pin Tsao, Wen-Yuan Chen, Chun-Fu Cheng, Chih-Ching Wang
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Publication number: 20140103438Abstract: A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.Type: ApplicationFiled: December 17, 2013Publication date: April 17, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Ching WANG, Jon-Hsu HO, Ching-Fang HUANG, Wen-Hsing HSIEH, Tsung-Hsing YU, Yi-Ming SHEU, Ken-Ichi GOTO, Zhiqiang WU
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Publication number: 20140051268Abstract: A male connector having an electrostatic discharge (ESD) function includes a metal portion, an insulating portion and a cable. The metal portion is inserted into a female connector. One end of the insulating portion is connected to the metal portion and another end of the insulating portion is connected to the cable. The cable includes a plurality of sub-cables and a grounded metal layer. The metal layer surrounds the sub-cables, and is in electrical contact with the metal portion. Static electricity on the metal portion is conducted to ground via the metal layer.Type: ApplicationFiled: August 13, 2013Publication date: February 20, 2014Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: CHIH-CHING WANG, YU-HUA HO
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Patent number: 8623716Abstract: A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.Type: GrantFiled: November 3, 2011Date of Patent: January 7, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Ching Wang, Jon-Hsu Ho, Ching-Fang Huang, Wen-Hsing Hsieh, Tsung-Hsing Yu, Yi-Ming Sheu, Ken-Ichi Goto, Zhiqiang Wu
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Publication number: 20130126981Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.Type: ApplicationFiled: November 22, 2011Publication date: May 23, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jon-Hsu HO, Chih-Ching WANG, Ching-Fang HUANG, Wen-Hsing HSIEH, Tsung-Hsing YU, Yi-Ming SHEU, Chih-Chieh YEH, Ken-Ichi GOTO, Zhiqiang WU
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Publication number: 20130113042Abstract: A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.Type: ApplicationFiled: November 3, 2011Publication date: May 9, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Ching Wang, Jon-Hsu Ho, Ching-Fang Huang, Wen-Hsing Hsieh, Tsung-Hsing Yu, Yi-Ming Sheu, Ken-Ichi Goto, Zhiqiang Wu
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Publication number: 20130056795Abstract: System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.Type: ApplicationFiled: December 22, 2011Publication date: March 7, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zhiqiang Wu, Ken-Ichi Goto, Wen-Hsing Hsieh, Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang
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Publication number: 20120119298Abstract: A method of forming an integrated circuit includes forming a plurality of gate structures longitudinally arranged along a first direction over a substrate. A plurality of angle ion implantations are performed to the substrate. Each of the angle ion implantations has a respective implantation angle with respect to a second direction. The second direction is substantially parallel with a surface of the substrate and substantially orthogonal to the first direction. Each of the implantation angles is substantially larger than 0°.Type: ApplicationFiled: November 11, 2010Publication date: May 17, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Zhiqiang WU, Yi-Ming SHEU, Tsung-Hsing YU, Kuan-Lun CHENG, Chih-Pin TSAO, Wen-Yuan CHEN, Chun-Fu CHENG, Chih-Ching WANG
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Patent number: 8180008Abstract: The present invention discloses a method for single-wire transmission without clock synchronization, comprising: providing three states; defining a spacing bit by a first state of the three states; and defining data signals, a start signal and an end signal by combinations of the second and third states of the three states.Type: GrantFiled: May 12, 2007Date of Patent: May 15, 2012Assignee: Richtek Technology CorporationInventors: Chih-Ching Wang, Jing-Meng Liu, Dah-Chih Lin
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Patent number: 7436837Abstract: The packet forwarding device and method of the invention assign a virtual port number to each peripheral interface. The device and method can recognize and process the packets coming from or transferred to the virtual port according to the packet direct forward function of the forward device. Thus, the device and method can process the packets that are inputted to or outputted from the peripheral interface and the network device connected to the peripheral interface in a manner similar to the typical method for processing the packets that are only inputted to or outputted from the physical port.Type: GrantFiled: October 4, 2004Date of Patent: October 14, 2008Assignee: Realtek Semiconductor Corp.Inventors: Yu-Zuong Chou, James Lin, Chih-Ching Wang, Chun-Feng Liu, Jin-Ru Chen
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Publication number: 20080080652Abstract: The present invention discloses a method for single-wire transmission without clock synchronization, comprising: providing three states; defining a spacing bit by a first state of the three states; and defining data signals, a start signal and an end signal by combinations of the second and third states of the three states.Type: ApplicationFiled: May 12, 2007Publication date: April 3, 2008Inventors: Chih-Ching Wang, Jing-Meng Liu, Dah-Chih Lin
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Patent number: 7149931Abstract: A method and networking apparatus for providing fault tolerance to memory are disclosed. The networking apparatus contains a first memory for storing host/port relationships, a second memory for indicating the status of the first memory, and a processor coupled to the memories for manipulating the memories. Furthermore, the claimed invention may also include an optional third memory for serving as a secondary site for storing information regarding host/port relationships.Type: GrantFiled: February 25, 2004Date of Patent: December 12, 2006Assignee: Realtek Semiconductor Corp.Inventors: Chang-Lien Wu, Chih-Ching Wang
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Publication number: 20050210205Abstract: A method for forming a linked list with defective memory in an electronic device is disclosed. The method includes the steps of: performing at least a built-in self test (BIST) on a memory of the electronic device; and forming or updating the linked list of the electronic device according to at least a result of the BIST; whereby the linked list of the electronic device does not correspond to any defective memory sections.Type: ApplicationFiled: March 17, 2004Publication date: September 22, 2005Inventors: Chang-Lien Wu, Chih-Ching Wang
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Publication number: 20050193234Abstract: A method and networking apparatus for providing fault tolerance to memory are disclosed. The networking apparatus contains a first memory for storing host/port relationships, a second memory for indicating the status of the first memory, and a processor coupled to the memories for manipulating the memories. Furthermore, the claimed invention may also include an optional third memory for serving as a secondary site for storing information regarding host/port relationships.Type: ApplicationFiled: February 25, 2004Publication date: September 1, 2005Inventors: Chang-Lien Wu, Chih-Ching Wang
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Publication number: 20050086395Abstract: The packet forwarding device and method of the invention assign a virtual port number to each peripheral interface. The device and method can recognize and process the packets coming from or transferred to the virtual port according to the packet direct forward function of the forward device. Thus, the device and method can process the packets that are inputted to or outputted from the peripheral interface and the network device connected to the peripheral interface in a manner similar to the typical method for processing the packets that are only inputted to or outputted from the physical port.Type: ApplicationFiled: October 4, 2004Publication date: April 21, 2005Inventors: Yu-Zuong Chou, James Lin, Chih-Ching Wang, Chun-Feng Liu, Jin-Ru Chen