Patents by Inventor Chih-Chung Chen

Chih-Chung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210020507
    Abstract: A method for fabricating a multi-layered wafer includes depositing a metal liner following by a seed layer including a metal in a trench arranged in an inter-metal dielectric (IMD). An end of the trench contacts a metal via of an interconnect structure. Heat is applied to drive the metal of the seed layer into the IMD and form a barrier layer along a sidewall of the trench.
    Type: Application
    Filed: July 19, 2019
    Publication date: January 21, 2021
    Inventors: Hsueh-Chung Chen, Junli Wang, Somnath Ghosh, Chih-Chao Yang, Lawrence A. Clevenger
  • Patent number: 10885914
    Abstract: The speech correction system includes a storage device and a processing device. The storage device stores a first database. The processing device includes an audio receiver, a speech recognition engine, a calculation module, and a determination module. The audio receiver receives multiple voice inputs. The speech recognition engine recognizes the voice inputs, generates multiple candidate vocabularies corresponding to each of the voice inputs, and generates a vocabulary probability corresponding to each of the candidate vocabularies. The calculation module performs a specific operation on the vocabulary probabilities corresponding to the same candidate vocabulary, to generate a plurality of corresponding operation results. The determination module determines whether each of the operation results is greater than a score threshold, and stores at least one output result that is greater than the score threshold to the first database.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: January 5, 2021
    Assignee: QUANTA COMPUTER INC.
    Inventors: Kuan-Chung Chen, Chih-Wei Sung, Yu-Cheng Chien, Yi-Ling Chen
  • Patent number: 10886307
    Abstract: The present disclosure is related to an electronic device that includes a display area and a non-display area. The electronic device includes a supporting substrate, a flexible substrate, a first organic insulating layer, a first conductive layer, a second conductive layer, a second organic insulating layer, and a resilient structure. The flexible substrate is disposed on the supporting substrate. The first organic insulating layer is disposed on the flexible substrate. The first conductive layer is disposed on the first organic insulating layer. The second conductive layer is disposed on the first conductive layer. The second organic insulating layer is disposed on the second conductive layer. The resilient structure includes resilient elements disposed between the first conductive layer and the second conductive layer. The first conductive layer alternately contacts the second conductive layer and the resilient elements.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: January 5, 2021
    Assignee: INNOLUX CORPORATION
    Inventors: Ti-Chung Chang, Chih-Chieh Wang, Chien-Chih Chen
  • Publication number: 20200411514
    Abstract: A semiconductor device and method are provided whereby a series of spacers are formed in a first region and a second region of a substrate. The series of spacers in the first region are patterned while the series of spacers in the second region are protected in order to separate the properties of the spacers in the first region from the properties of the spacers in the second region.
    Type: Application
    Filed: February 3, 2020
    Publication date: December 31, 2020
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chi-Sheng Lai, Chih-Han Lin, Wei-Chung Sun, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 10871713
    Abstract: A method of controlling reticle masking blade positioning to minimize the impact on critical dimension uniformity includes determining a target location of a reticle masking blade relative to a reflective reticle and positioning the reticle masking blade at the target location. A position of the reticle masking blade is monitored during an imaging operation. The position of the reticle masking blade is compared with the target location and the position of the reticle masking blade is adjusted if the position of the reticle masking blade is outside a tolerance of the target location.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Wen Cho, Fu-Jye Liang, Chun-Kuang Chen, Chih-Tsung Shih, Li-Jui Chen, Po-Chung Cheng, Chin-Hsiang Lin
  • Patent number: 10866850
    Abstract: A memory device includes a memory module and a control module. The control module is coupled to the memory module and is configured to store data into the memory module according to a first mapping table. The control module includes a storing unit and a guaranteeing unit. The storing unit is configured to store the first mapping table. The guaranteeing unit is coupled to the storing unit and is configured to determine whether the first mapping table is correct or not. The guaranteeing unit is further configured to issue an error signal in a state where the first mapping table is incorrect.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: December 15, 2020
    Assignee: RAYMX MICROELECTRONICS CORP.
    Inventors: Yen-Chung Chen, Cheng-Yu Chen, Chih-Ching Chien
  • Patent number: 10868148
    Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: December 15, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Chang Lin, Bo-Han Huang, Chih-Chung Chen, Chun-Hsien Lin, Shih-Hung Tsai, Po-Kuang Hsieh
  • Publication number: 20200381354
    Abstract: Techniques for fabricating a metallic interconnect include forming a first metallization layer that includes a first dielectric layer, a first metallic layer formed in the first dielectric layer and a first capping layer formed on the first dielectric layer and the first metallic layer and forming a second metallization layer that includes a second dielectric layer, a second metallic layer formed in the second dielectric layer and a second capping layer formed on the second dielectric layer and the second metallic layer. A channel is etched in the second capping layer, second dielectric layer, and first capping layer that exposes a portion of the first metallic layer and a portion of the second metallic layer. A metallic interconnect structure is formed in the channel in contact with the exposed portion of the first metallic layer and the exposed portion of the second metallic layer.
    Type: Application
    Filed: May 29, 2019
    Publication date: December 3, 2020
    Inventors: Yann Mignot, Hosadurga Shobha, Hsueh-Chung Chen, Chih-Chao Yang
  • Patent number: 10852649
    Abstract: Embodiments described herein provide a method for cleaning contamination from sensors in a lithography tool without requiring recalibrating the lithography tool. More particularly, embodiments described herein teach cleaning the sensors using hydrogen radicals for a short period while the performance drifting is still above the drift tolerance. After a cleaning process described herein, the lithography tool can resume production without recalibration.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zi-Wen Chen, Po-Chung Cheng, Chih-Tsung Shih, Li-Jui Chen, Shih-Chang Shih
  • Publication number: 20200350306
    Abstract: A layout modification method for fabricating a semiconductor device is provided. Uniformity of critical dimensions of a first portion and a second portion in a patterned layer are calculated by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the second portion equals a penumbra size of the exposure manufacturing process, and the penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. Non-uniformity between the first and second portions of the patterned layer is compensated according to the uniformity of critical dimensions to generate a modified layout. The patterned layer includes a plurality of absorbers, and a first width of the absorbers is the first portion is less than a second width of the absorbers in the second portion the second portion.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 5, 2020
    Inventors: Hung-Wen CHO, Fu-Jye LIANG, Chun-Kuang CHEN, Chih-Tsung SHIH, Li-Jui CHEN, Po-Chung CHENG, Chin-Hsiang LIN
  • Publication number: 20200348586
    Abstract: A method for collecting information in image-error compensation is provided. The method includes providing a reticle having a first image structure and a second image structure; moving a light shading member to control a first exposure field; projecting a light over the first exposure field; recording an image of the first image structure after the light is projected; moving the light shading member to control a second exposure field; projecting the light over the second exposure field; and recording an image of the second image structure after the light is projected.
    Type: Application
    Filed: July 13, 2020
    Publication date: November 5, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Wen CHO, Fu-Jye LIANG, Chun-Kuang CHEN, Chih-Tsung SHIH, Li-Jui CHEN, Po-Chung CHENG, Chin-Hsiang LIN
  • Patent number: 10826493
    Abstract: A gate driving circuit for providing a high driving voltage includes a first N-type high-voltage transistor and a second N-type high-voltage transistor connected in series between a driving voltage output node and a system low-voltage source. A voltage difference between a system high-voltage source and the system low-voltage source is greater than a withstand voltage of the first or second N-type high-voltage transistor. When the driving voltage output node is to output a system high voltage, the first N-type high-voltage transistor and the second N-type high-voltage transistor are turned off. Deep N-type well regions of the first N-type high-voltage transistor and the second N-type high-voltage transistor are applied with a first bias voltage. A voltage difference between the first bias voltage and the system low-voltage source is smaller than an interface breakdown voltage between the deep N-type well region and a P-type well region of the second N-type high-voltage transistor.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: November 3, 2020
    Assignee: ITE Tech. Inc.
    Inventors: Yi-Chung Chou, Chih-Yuan Kuo, Dong-Shan Chen
  • Publication number: 20200343269
    Abstract: A pixel array substrate including a substrate, a plurality of pixel structures and a scan device is provided. The pixel structures are arranged on the substrate along a first direction. Each pixel structure includes a data line, an active device and a pixel electrode. The active device has a semiconductor pattern, a source electrode and a drain electrode. The source electrode and the drain electrode are electrically connected to the data line and the pixel electrode respectively. The scan device includes a first and a second scan line. The first and the second scan line extend in the first direction and are electrically connected to each other. The active devices of the pixel structures are electrically connected to the first and the second scan line. The first and the second scan line respectively overlap two different regions of the semiconductor pattern of each active device.
    Type: Application
    Filed: October 8, 2019
    Publication date: October 29, 2020
    Applicant: Au Optronics Corporation
    Inventors: Chih-Chung Su, Yi-Wei Chen
  • Publication number: 20200328212
    Abstract: A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.
    Type: Application
    Filed: February 21, 2020
    Publication date: October 15, 2020
    Inventors: Guo-Huei WU, Jerry Chang Jui KAO, Chih-Liang CHEN, Hui-Zhong ZHUANG, Jung-Chan YANG, Lee-Chung LU, Xiangdong CHEN
  • Patent number: 10802961
    Abstract: An apparatus and a method for accessing a plurality of memory blocks is disclosed. The An apparatus comprises: a memory circuit configured to store a recording table, wherein the recording table corresponds to quality index of the plurality of memory blocks; and a control circuit configured to group the plurality of memory blocks to a first memory group and a second memory group according to the quality index; to enable to access the memory blocks in the first memory group, and to disable to access the memory blocks in the second memory group.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: October 13, 2020
    Assignee: RAYMX MICROELECTRONICS CORP.
    Inventors: Yen-Chung Chen, Chih-Ching Chien, Li-Chun Huang, Han-Ting Tsai, Wei-Ren Hsu
  • Patent number: 10792904
    Abstract: A method for bonding a first component to a second component includes placing the first and second components in a cavity. Each of the first and second components has a bonding portion, and the bonding portion of the first component faces the bonding portion of the second component. A supercritical fluid is then introduced into the cavity with a temperature of 40-400° C. and a pressure of 1,500-100,000 psi, and a pressure of 4-100,000 psi is applied on both the first and second components, assuring the bonding portion of the first component bond to the bonding portion of the second component. Moreover, a method for separating a first component from a second component includes placing a composite in a cavity. The composite includes the first component, the second component and a connecting layer by which the first component joins to the second component. The supercritical is then introduced into the cavity.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: October 6, 2020
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: Ting-Chang Chang, Chih-Cheng Shih, Ming-Hui Wang, Wen-Chung Chen, Chih-Yang Lin
  • Publication number: 20200296561
    Abstract: A method applied to a wireless Bluetooth audio communication system includes: providing an audio gateway of a first piconet to communicate with a master device in the first piconet and to transmit at least one packet of audio stream to the master device and a slave device; employing a first transceiver as the master device to receive the at least one packet of the audio stream from the audio gateway; and, employing a second transceiver as the slave device to receive the at least one packet of the audio stream from the audio gateway and to acknowledge the first transceiver whether the second transceiver has successfully received the at least one packet of the audio stream from the audio gateway.
    Type: Application
    Filed: June 3, 2020
    Publication date: September 17, 2020
    Inventors: Kuang-Hu Huang, Wei-Chung Peng, Jeng-Hong Chen, PETE HSINHSIANG LIU, De-Hao Tseng, Jing-Syuan Jia, Chih-Wei Sung, I-Ken Ho
  • Publication number: 20200296503
    Abstract: A speaker device includes an external housing, a sound guide structure, and a speaker unit. The sound guide structure is located in the external housing and has a paraboloid. The speaker unit is located in the external housing and configured to sound towards the paraboloid. The paraboloid has a focus. The speaker unit has a sound emitting surface. The center of the sound emitting surface is substantially coincident with the focus.
    Type: Application
    Filed: August 20, 2019
    Publication date: September 17, 2020
    Inventors: Chih-Hsiang HSU, Ching-Chung CHEN
  • Patent number: 10776011
    Abstract: A computing system including a memory, a processor and a solid state disk is provided. The memory stores a disk access driver program. The solid state disk includes a storage circuit and a control circuit. The control circuit includes a processing unit, a first access path and a second access path. The processing unit communicates with the processor through the first access path. The processor executes the driver program that enables the processor to process a disk access command for directly accessing the storage circuit of the solid state disk through the second access path.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: September 15, 2020
    Assignee: RAYMX MICROELECTRONICS CORP.
    Inventors: Cheng-Yu Chen, Chih-Ching Chien, Yen-Chung Chen
  • Patent number: 10770345
    Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a first polish stop layer above a memory device, in which the first polish stop layer has a first portion over the memory device and a second portion that is not over the memory device; removing the second portion of the first polish stop layer; depositing an inter-layer dielectric layer over the first polish stop layer after removing the second portion of the first polish stop layer; and polishing the inter-layer dielectric layer until reaching the first portion of the first polish stop layer.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Chang-Sheng Lin, Chien-Chung Huang, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Chih-Yuan Ting, Jyu-Horng Shieh