Abstract: An antenna structure includes a substrate, a radiator mounted at an upper portion of a front surface of the substrate, and a grounding element mounted at a lower portion of the front surface of the substrate. The radiator has a first radiating portion. A lower edge of the first radiating portion extends downward to form a second radiating portion. Two portions of a middle of the lower edge of the first radiating portion extend downward to form a third radiating portion and a feeding portion. A free end of the feeding portion is a feeding end. One side edge of the first radiating portion is recessed inward to form a recess. The grounding element has a first grounding portion and a second grounding portion. The first grounding portion and the second grounding portion are located to two sides of the feeding portion, respectively.

Abstract: An antenna structure includes a substrate, a radiator mounted at one end of a front surface of the substrate, and a grounding element mounted at the other end of the front surface of the substrate. The radiator has a first radiating portion. Two portions of a middle of one end edge of the first radiating portion extend horizontally to form a second radiating portion and a feeding portion. The feeding portion is located above the second radiating portion. A free end of the feeding portion is a feeding end. An upper portion of the other end edge of the first radiating portion extends opposite to the one end edge of the first radiating portion and extends along a rectangular spiral path to form a rectangular spiral third radiating portion.

Abstract: A multi-band antenna includes a lower grounding portion, a feed-in portion, a feeding point, an upper grounding portion, a first extending portion, a second extending portion, a third extending portion, a fourth extending portion, a fifth extending portion, a first branch, a second branch, a third branch and a loop portion. The feed-in portion, the first extending portion, the second extending portion, the third extending portion, the fourth extending portion and the first branch form a first radiation portion. The feed-in portion, the first extending portion, the second extending portion, the third extending portion, the fifth extending portion and the second branch form a second radiation portion. The feed-in portion, the first extending portion, the second extending portion and the third branch form a third radiation portion.

Abstract: An antenna structure includes a substrate, a radiator mounted at an upper portion of a front surface of the substrate, and a grounding element mounted at a lower portion of the front surface of the substrate. The radiator has a first radiating portion. A lower edge of the first radiating portion extends downward to form a second radiating portion. Two portions of a middle of the lower edge of the first radiating portion extend downward to form a third radiating portion and a feeding portion. A free end of the feeding portion is a feeding end. One side edge of the first radiating portion is recessed inward to form a recess. The grounding element has a first grounding portion and a second grounding portion. The first grounding portion and the second grounding portion are located to two sides of the feeding portion, respectively.

Abstract: An antenna structure includes a substrate, a radiator mounted at one end of a front surface of the substrate, and a grounding element mounted at the other end of the front surface of the substrate. The radiator has a first radiating portion. Two portions of a middle of one end edge of the first radiating portion extend horizontally to form a second radiating portion and a feeding portion. The feeding portion is located above the second radiating portion. A free end of the feeding portion is a feeding end. An upper portion of the other end edge of the first radiating portion extends opposite to the one end edge of the first radiating portion and extends along a rectangular spiral path to form a rectangular spiral third radiating portion.

Abstract: A multi-band antenna includes a grounding portion, a feed-in portion, a feeding point, a first radiation portion, a second radiation portion, a third radiation portion and a fourth radiation portion. The feed-in portion has a first end edge, a second end edge, a first side edge and a second side edge. The feeding point is disposed at the feed-in portion. The first radiation portion is extended from the grounding portion. The second radiation portion is extended from the second end edge. The third radiation portion is extended from the first end edge. The fourth radiation portion is extended from an upper portion of the first end edge and an upper portion of the second end edge.

Abstract: A multi-band antenna includes a lower grounding portion, a feed-in portion, a feeding point, an upper grounding portion, a first extending portion, a second extending portion, a third extending portion, a fourth extending portion, a fifth extending portion, a first branch, a second branch, a third branch and a loop portion. The feed-in portion, the first extending portion, the second extending portion, the third extending portion, the fourth extending portion and the first branch form a first radiation portion. The feed-in portion, the first extending portion, the second extending portion, the third extending portion, the fifth extending portion and the second branch form a second radiation portion. The feed-in portion, the first extending portion, the second extending portion and the third branch form a third radiation portion.

Abstract: A multi-band antenna includes a grounding portion, a feed-in portion, a feeding point, a first radiation portion, a second radiation portion, a third radiation portion and a fourth radiation portion. The feed-in portion has a first end edge, a second end edge, a first side edge and a second side edge. The feeding point is disposed at the feed-in portion. The first radiation portion is extended from the grounding portion. The second radiation portion is extended from the second end edge. The third radiation portion is extended from the first end edge. The fourth radiation portion is extended from an upper portion of the first end edge and an upper portion of the second end edge.

Abstract: A metal-oxide-semiconductor (MOS) transistor includes a substrate. The substrate has a plurality of trenches extending along a first direction and located on a top portion of the substrate. A gate structure line is located on the substrate and extends along a second direction intersecting with the first direction and crossing over the trenches. A first doped line is located in the substrate, located at a first side of the gate structure line, and crosses over the trenches. A second doped line is located in the substrate, located at a second side of the gate structure line, and crosses over the trenches.

Abstract: A gate oxide forming process includes the following steps. A substrate including a first area and a second area is provided. A first oxide layer, a silicon containing cap layer and a second oxide layer on the substrate of the first area and the second area are sequentially and blanketly formed. The silicon containing cap layer and the second oxide layer in the first area are removed. An oxidation process is performed to oxidize the silicon containing cap layer and a gate oxide layer is formed in the second area.

Abstract: A gate oxide forming process includes the following steps. A substrate including a first area and a second area is provided. A first oxide layer, a silicon containing cap layer and a second oxide layer on the substrate of the first area and the second area are sequentially and blanketly formed. The silicon containing cap layer and the second oxide layer in the first area are removed. An oxidation process is performed to oxidize the silicon containing cap layer and a gate oxide layer is formed in the second area.

Abstract: A metal-oxide-semiconductor (MOS) transistor includes a substrate. The substrate has a plurality of trenches extending along a first direction and located on a top portion of the substrate. A gate structure line is located on the substrate and extends along a second direction intersecting with the first direction and crossing over the trenches. A first doped line is located in the substrate, located at a first side of the gate structure line, and crosses over the trenches. A second doped line is located in the substrate, located at a second side of the gate structure line, and crosses over the trenches.

Abstract: A contact lens with functional components and products thereof are disclosed, wherein at least one bonding agent is added to the polymeric matrix material of the lens body. The bonding agent can effectively integrate with various kinds of functional components to improve the characteristics of the lens body, increase the comfort of wearing the contact lens, and enhance the ability of water retention. While the user wears the contact lens, the contact lens can release the functional components persistently. Therefore, the present invention can relieve irritations caused by dust, dirt, smoke, and/or pollution from the environment.

Abstract: Method for fabricating semiconductor device, including semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.

Abstract: A semiconductor structure and a manufacturing method of a semiconductor structure are provided. The semiconductor structure includes a semiconductor substrate, a gate, a first diffusion region and a second diffusion region. The gate is disposed on the semiconductor substrate and extends along a first direction. The first diffusion region is formed in the semiconductor substrate, and the second diffusion region is formed in the first diffusion region. The first diffusion region has a first portion located underneath the gate and a second portion protruded from a lateral side of the gate, the first portion has a first length parallel to the first direction, the second portion has a second length parallel to the first direction, and the first length is larger than the second length.

Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

Abstract: Method for fabricating semiconductor device, including semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.

Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

Abstract: A transistor structure including a substrate, a transistor device, a split buried layer, and a second buried layer is provided. The substrate has a device region. The transistor device is located in the device region. The split buried layer is located under the transistor device in the substrate and includes first buried layers separated from each other. The second buried layer is located under the split buried layer in the substrate and connects the first buried layers. The second buried layer and the split buried layer have a first conductive type. The transistor structure may have a higher breakdown voltage.

Abstract: A semiconductor device including a substrate and a shallow trench isolation (STI) structure is provided. The substrate has a first voltage area and a second voltage area. A top surface of the substrate in the second voltage area is higher than a top surface of the substrate in the first voltage area, and a trench is defined in the substrate in between the first and second voltage area. The STI structure is located in the substrate within the trench, wherein a first portion of the STI structure is located in the first voltage area, a second portion of the STI structure is located in the second voltage area, and a step height difference exist in between a bottom surface of the first portion of the STI structure in the first voltage area and a bottom surface of the second portion of the STI structure in the second voltage area.