Patents by Inventor Chih-Chung Wang

Chih-Chung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10396157
    Abstract: A semiconductor device includes semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: August 27, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Shin-Hung Li, Kuan-Chuan Chen, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Publication number: 20190245041
    Abstract: A transistor structure including a substrate, a transistor device, a split buried layer, and a second buried layer is provided. The substrate has a device region. The transistor device is located in the device region. The split buried layer is located under the transistor device in the substrate and includes first buried layers separated from each other. The second buried layer is located under the split buried layer in the substrate and connects the first buried layers. The second buried layer and the split buried layer have a first conductive type. The transistor structure may have a higher breakdown voltage.
    Type: Application
    Filed: March 16, 2018
    Publication date: August 8, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Yen-Ming Chen, Chiu-Ling Lee, Min-Hsuan Tsai, Chiu-Te Lee, Chih-Chung Wang
  • Publication number: 20190245038
    Abstract: A semiconductor device includes semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.
    Type: Application
    Filed: March 6, 2018
    Publication date: August 8, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Shin-Hung Li, Kuan-Chuan Chen, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Patent number: 10314180
    Abstract: A display device includes a display panel, a bezel, at least one flexible circuit board, and a rigid circuit board. The display panel includes a display surface. The bezel includes a top wall, a bottom wall, and a side wall between the top wall and the bottom wall. The top wall is configured to support the display panel. The flexible circuit board includes a first portion, a second portion, and a connection portion between the first portion and the second portion. The first portion of the flexible circuit board is connected to the display panel. At least part of the rigid circuit board overlaps and faces the bottom wall of the bezel. The rigid circuit board includes an edge extending outwardly and beyond the side wall. The edge of the rigid circuit board includes at least one recess. The second portion of the flexible circuit board is connected to the rigid circuit board. At least part of the connection portion of the flexible circuit board is accommodated in the recess.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: June 4, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventor: Chih-Chung Wang
  • Publication number: 20190157421
    Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.
    Type: Application
    Filed: January 28, 2019
    Publication date: May 23, 2019
    Inventors: Chia-Ling Wang, Ping-Hung Chiang, Chang-Po Hsiung, Chia-Wen Lu, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Publication number: 20190157418
    Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.
    Type: Application
    Filed: December 18, 2017
    Publication date: May 23, 2019
    Inventors: Chia-Ling Wang, Ping-Hung Chiang, Chang-Po Hsiung, Chia-Wen Lu, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Patent number: 10290718
    Abstract: A metal-oxide semiconductor transistor includes a substrate, a gate insulating layer disposed on a surface of the substrate, and a metal gate disposed on the gate insulating layer, wherein at least one of the length or the width of the metal gate is greater than or equal to approximately 320 nanometers, and the metal gate has at least one plug hole. The metal-oxide semiconductor transistor further includes at least one insulating plug disposed in the plug hole and two diffusion regions disposed respectively at two sides of the metal gate in the substrate.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: May 14, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Ching-Chung Yang, Wen-Fang Lee, Nien-Chung Li, Chih-Chung Wang
  • Patent number: 10276652
    Abstract: A schottky diode includes a schottky junction, an ohmic junction, a first isolation structure and a plurality of doped regions. The schottky junction includes a first well in a substrate and a first electrode contacting the first well. The ohmic junction includes a junction region in the first well and a second electrode contacting the junction region. The first isolation structure is disposed in the substrate and separates the schottky junction from the ohmic junction. The doped regions are located in the first well and under the schottky junction, wherein the doped regions separating from each other constitute a top-view profile of concentric circles.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: April 30, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Hua Yang, Ke-Feng Lin, Ming-Tsung Lee, Shih-Teng Huang, Chih-Chung Wang, Chiu-Te Lee, Shu-Wen Lin
  • Publication number: 20190115469
    Abstract: A semiconductor structure and a manufacturing method of a semiconductor structure are provided. The semiconductor structure includes a semiconductor substrate, a gate, a first diffusion region and a second diffusion region. The gate is disposed on the semiconductor substrate and extends along a first direction. The first diffusion region is formed in the semiconductor substrate, and the second diffusion region is formed in the first diffusion region. The first diffusion region has a first portion located underneath the gate and a second portion protruded from a lateral side of the gate, the first portion has a first length parallel to the first direction, the second portion has a second length parallel to the first direction, and the first length is larger than the second length.
    Type: Application
    Filed: August 14, 2018
    Publication date: April 18, 2019
    Inventors: Shin-Hung Li, Kuan-Chuan Chen, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Publication number: 20190103460
    Abstract: A semiconductor transistor device is provided. The semiconductor transistor device includes a semiconductor substrate, a gate structure, a first isolation structure, a first doped region, and a first extra-contact structure. The gate structure is disposed on the semiconductor substrate, and the semiconductor substrate has a first region and a second region respectively located on two opposite sides of the gate structure. The first isolation structure and the first doped region are disposed in the first region of the semiconductor substrate. The first extra-contact structure is disposed on the semiconductor structure. The first extra-contact structure is located between the gate structure and the first doped region and penetrating into the first isolation structure in the first region of the semiconductor substrate, and the first doped region is electrically coupled to the first extra-contact structure.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Chang-Po Hsiung, Ping-Hung Chiang, Chia-Lin Wang, Chia-Wen Lu, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Patent number: 10204996
    Abstract: A method of forming a gate layout includes providing a gate layout design diagram comprising at least one gate pattern, disposing at least one insulating plug pattern in the gate pattern for producing a modified gate layout in a case where any one of a length and a width of the gate pattern is greater than or equal to a predetermined size, and outputting and manufacturing the modified gate layout onto a photomask. The predetermined size is determined by a process ability limit, and the process ability limit is a smallest gate size causing gate dishing when a chemical mechanical polishing process is performed to a gate.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: February 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Ching-Chung Yang, Wen-Fang Lee, Nien-Chung Li, Chih-Chung Wang
  • Patent number: 10152964
    Abstract: Non-limiting examples described herein relate to processing for transcoding textual content into audio signals. In some examples, transcoding services are provided over a distributed network, for example, through an interaction between a client device and a server device. For instance, a client device may transmit a selection of a document to a server device. The server device may access a document source for the document and transcode content from the document source into speech. The server device may transmit the transcoded content to the client device, for example, where the client device may output the transcoded content. For instance, the transcoded content may be an audio file that is streamed by the client device.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: December 11, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sheng-Yao Shih, Yun-Chiang Kung, Chiwei Che, Chih-Chung Wang
  • Patent number: 10141398
    Abstract: A semiconductor structure includes a HV NMOS structure. The HV NMOS structure includes a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. The source region and the drain region are separated from each other. The channel region is disposed between the source region and the drain region. The channel region has a channel direction from the source region toward the drain region. The gate dielectric is disposed on the channel region and on portions of the source region and the drain region. The gate electrode is disposed on the gate dielectric. The gate electrode includes a first portion of n-type doping and two second portions of p-type doping. The two second portions are disposed at two sides of the first portion. The two second portions have an extending direction perpendicular to the channel direction.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: November 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Hua Tsai, Jung Han, Chin-Chia Kuo, Wen-Fang Lee, Chih-Chung Wang
  • Patent number: 10084083
    Abstract: A semiconductor structure and a manufacturing method of a semiconductor structure are provided. The semiconductor structure includes a semiconductor substrate, a gate, a first diffusion region and a second diffusion region. The gate is disposed on the semiconductor substrate and extends along a first direction. The first diffusion region is formed in the semiconductor substrate, and the second diffusion region is formed in the first diffusion region. The first diffusion region has a first portion located underneath the gate and a second portion protruded from a lateral side of the gate, the first portion has a first length parallel to the first direction, the second portion has a second length parallel to the first direction, and the first length is larger than the second length.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: September 25, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shin-Hung Li, Kuan-Chuan Chen, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Publication number: 20180233556
    Abstract: A semiconductor device including a substrate and a shallow trench isolation (STI) structure is provided. The substrate has a first voltage area and a second voltage area. A top surface of the substrate in the second voltage area is higher than a top surface of the substrate in the first voltage area, and a trench is defined in the substrate in between the first and second voltage area. The STI structure is located in the substrate within the trench, wherein a first portion of the STI structure is located in the first voltage area, a second portion of the STI structure is located in the second voltage area, and a step height difference exist in between a bottom surface of the first portion of the STI structure in the first voltage area and a bottom surface of the second portion of the STI structure in the second voltage area.
    Type: Application
    Filed: April 12, 2018
    Publication date: August 16, 2018
    Applicant: United Microelectronics Corp.
    Inventors: Chang-Po Hsiung, Ping-Hung Chiang, Shih-Chieh Pu, Chia-Lin Wang, Nien-Chung Li, Wen-Fang Lee, Shih-Yin Hsiao, Chih-Chung Wang
  • Patent number: 10018328
    Abstract: A light emitting module includes a lens and first and second light sources aligning with the lens. The lens includes a first biconcave section having a first light-entrance concave surface and a first light-exit concave surface, a second biconcave section having a second light-entrance concave surface and a second light-exit concave surface, and a shared section having a light-exit shared surface. A tangent slope of the shared section where the light-exit shared surface is connected to the first light-exit concave surface is less than a tangent slope of the first biconcave section where the first light-exit concave surface is connected to the light-exit shared surface. A tangent slope of the shared section where the light-exit shared surface is connected to the second light-exit concave surface is larger than a tangent slope of the second biconcave section where the second light-exit concave surface is connected to the light-exit shared surface.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: July 10, 2018
    Assignee: VIVOTEK INC.
    Inventors: Li-Shan Shih, Yi-Hsin Yeh, Chih-Chung Wang, Chih-Hung Chang
  • Publication number: 20180184530
    Abstract: A display device includes a display panel, a bezel, at least one flexible circuit board, and a rigid circuit board. The display panel includes a display surface. The bezel includes a top wall, a bottom wall, and a side wall between the top wall and the bottom wall. The top wall is configured to support the display panel. The flexible circuit board includes a first portion, a second portion, and a connection portion between the first portion and the second portion. The first portion of the flexible circuit board is connected to the display panel. At least part of the rigid circuit board overlaps and faces the bottom wall of the bezel. The rigid circuit board includes an edge extending outwardly and beyond the side wall. The edge of the rigid circuit board includes at least one recess. The second portion of the flexible circuit board is connected to the rigid circuit board. At least part of the connection portion of the flexible circuit board is accommodated in the recess.
    Type: Application
    Filed: November 20, 2017
    Publication date: June 28, 2018
    Inventor: Chih-Chung WANG
  • Patent number: 9997643
    Abstract: A diode structure includes a rectangular first doping region, and a second doping region surrounds the first doping region wherein the first doping region and the second doping region are separated by a first isolation structure. A third doping region surrounds the second doping region wherein the second doping region and the third doping region are separated by a second isolation structure. The first isolation structure, the second doping region, the second isolation structure and the third doping region are arranged in a quadruple concentric rectangular ring surrounding the first doping region.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: June 12, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ke-Feng Lin, Hsuan-Po Liao, Ming-Shun Hsu, Chih-Chung Wang, Chiu-Te Lee, Shih-Teng Huang
  • Patent number: 9985129
    Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: May 29, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Kuan-Liang Liu, Ching-Chung Yang, Kai-Kuen Chang, Ping-Hung Chiang, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Patent number: 9972678
    Abstract: A method of forming a semiconductor device is provided including the following steps. A substrate having a first voltage area and a second voltage area is provided. A first oxide layer is formed in the first voltage area. The first oxide layer is removed to form a recess in the first voltage area. A shallow trench isolation (STI) structure is formed in the substrate, wherein a first portion of the STI structure is located in the first voltage area and a second portion of the STI structure is located in the second voltage area, a top surface of the STI structure is higher than the top surface of the substrate, and a bottom surface of the first portion of the STI structure in the first voltage area is lower than a bottom surface of the second portion of the STI structure in the second voltage area.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: May 15, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Chang-Po Hsiung, Ping-Hung Chiang, Shih-Chieh Pu, Chia-Lin Wang, Nien-Chung Li, Wen-Fang Lee, Shih-Yin Hsiao, Chih-Chung Wang