Abstract: The present invention provides a method of fabricating a HV MOS transistor device, including forming a deep well in a substrate, and the deep well; forming a first doped region in the deep well, and the first doped region, wherein a doping concentration of the first doped region and a doping concentration of the deep well in at least one electric field concentration region has a first ratio, the doping concentration of the first doped region and the doping concentration of the deep well outside the electric field concentration region has a second ratio, and the first ratio is greater than the second ratio; and forming a high voltage well in the substrate, and forming a second doped region and a third doped region respectively in the deep well and in the high voltage well.

Abstract: The present invention provides and apparatus for distinguishing falls from activities of daily living (ADLs). First, the human movements and muscle activities would be obtained by an electromyography measuring unit and/or an inertia measuring unit to record ADLs, and falls would be distinguished from ADLs to trigger the protecting devices in time to prevent or decrease injury. In addition, the apparatus would be preset for different operational conditions to adapt different users by a setting unit to increase accuracy. Finally, the moving distance and the direction of the user would be obtained by the electromyography measuring unit and/or the inertia measuring unit to obtain the location thereof in an interior space.

Abstract: A power array with a staggered arrangement for improving on-resistance and safe operating area of a device is provided. Each power array includes two or more rows with a plurality of parallel device units arranged along the row. Each device unit includes a source region, a drain region, and a gate disposed between the source region and the drain region, wherein each drain region is offset from the adjacent drain region of adjacent rows in a row direction.

Abstract: A layout pattern of an implant layer includes at least a linear region and at least a non-linear region. The linear region includes a plurality of first patterns to accommodate first dopants and the non-linear region includes a plurality of second patterns to accommodate the first dopants. The linear region abuts the non-linear region. Furthermore, a pattern density of the first patterns in the linear region is smaller than a pattern density of the second patterns in the non-linear region.

Abstract: A lateral double-diffused metal-oxide-semiconductor transistor device includes a substrate having at least a shallow trench isolation formed therein, an epitaxial layer encompassing the STI in the substrate, a gate, and a drain region and a source region formed in the substrate at respective two sides of the gate. The epitaxial layer, the source region and the drain region include a first conductivity type. The gate includes a first portion formed on the substrate and a second portion extending into the STI.

Abstract: The present invention provides a high voltage metal-oxide-semiconductor transistor device including a substrate, a deep well, and a doped region. The substrate and the doped region have a first conductive type, and the substrate has at least one electric field concentration region. The deep well has a second conductive type different from the first conductive type. The deep well is disposed in the substrate, and the doped region is disposed in the deep well. The doping concentrations of the doped region and the deep well in the electric field have a first ratio, and the doping concentrations of the doped region and the deep well outside the electric field have a second ratio. The first ratio is greater than the second ratio.

Abstract: A high voltage metal-oxide-semiconductor (HV MOS) transistor device includes a substrate, a drifting region formed in the substrate, a plurality of isolation structures formed in the drift region and spaced apart from each other by the drift region, a plurality of doped islands respectively formed in the isolation structures, a gate formed on the substrate, and a source region and a drain region formed in the substrate at respective two sides of the gate. The gate covers a portion of each isolation structure. The drift region, the source region, and the drain region include a first conductivity type, the doped islands include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract: A power array with a staggered arrangement for improving on-resistance and safe operating area of a device is provided. Each power array includes two or more rows with a plurality of parallel device units arranged along the row. Each device unit includes a source region, a drain region, and a gate disposed between the source region and the drain region, wherein each drain region is offset from the adjacent drain region of adjacent rows in a row direction.

Abstract: A high voltage metal-oxide-semiconductor (HV MOS) transistor device includes a substrate, a drifting region formed in the substrate, a plurality of isolation structures formed in the drift region and spaced apart from each other by the drift region, a plurality of doped islands respectively formed in the isolation structures, a gate formed on the substrate, and a source region and a drain region formed in the substrate at respective two sides of the gate. The gate covers a portion of each isolation structure. The drift region, the source region, and the drain region include a first conductivity type, the doped islands include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract: A high voltage semiconductor device includes a substrate, an insulating layer positioned on the substrate, and a silicon layer positioned on the insulating layer. The silicon layer further includes at least a first doped strip, two terminal doped regions formed respectively at two opposite ends of the silicon layer and electrically connected to the first doped strip, and a plurality of second doped strips. The first doped strip and the terminal doped regions include a first conductivity type, the second doped strips include a second conductivity type, and the first conductivity type and the second conductivity type are complementary. The first doped strip and the second doped strips are alternately arranged.

Abstract: The present invention provides and apparatus for distinguishing falls from activities of daily living (ADLs). First, the human movements and muscle activities would be obtained by an electromyography measuring unit and/or an inertia measuring unit to record ADLs, and falls would be distinguished from ADLs to trigger the protecting devices in time to prevent or decrease injury. In addition, the apparatus would be preset for different operational conditions to adapt different users by a setting unit to increase accuracy. Finally, the moving distance and the direction of the user would be obtained by the electromyography measuring unit and/or the inertia measuring unit to obtain the location thereof in an interior space.

Abstract: A method of fabricating a solar cell includes the following steps. At first, a substrate including a doped layer is provided. Subsequently, a patterned material layer partially overlapping the doped layer is formed on the substrate, and a first metal layer is conformally formed on the patterned material layer and the doped layer. Furthermore, a patterned mask layer totally overlapping the patterned material layer is formed on the first metal layer, and a second metal layer is formed on the doped layer not overlapped by the patterned material layer. Then, the patterned mask layer, the first metal layer between the patterned mask layer and the patterned material layer and a part of the patterned material layer are removed.

Abstract: A transistor device and a manufacturing method thereof are provided. The transistor device includes a substrate, a first well, a second well, a shallow trench isolation (STI), a source, a drain and a gate. The first well is disposed in the substrate. The second well is disposed in the substrate. The STI is disposed in the second well. The STI has at least one floating diffusion island. The source is disposed in the first well. The drain is disposed in the second well. The electric type of the floating diffusion island is different from or the same with that of the drain. The gate is disposed above the first well and the second well, and partially overlaps the first well and the second well.

Abstract: A high voltage metal-oxide-semiconductor transistor device includes a substrate having an insulating region formed therein, a gate covering a portion of the insulating region and formed on the substrate, a source region and a drain region formed at respective sides of the gate in the substrate, a body region formed in the substrate and partially overlapped by the gate, and a first implant region formed in the substrate underneath the gate and adjacent to the body region. The substrate and body region include a first conductivity type. The source region, the drain region, and the first implant region include a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.

Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation. The bottom surface of the second portion of the conductive plug is covered by the isolation.

Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and extending down from the surface of the substrate, and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation.

Abstract: A layout pattern of an implant layer includes at least a linear region and at least a non-linear region. The linear region includes a plurality of first patterns to accommodate first dopants and the non-linear region includes a plurality of second patterns to accommodate the first dopants. The linear region abuts the non-linear region. Furthermore, a pattern density of the first patterns in the linear region is smaller than a pattern density of the second patterns in the non-linear region.

Abstract: A method for fabricating a high voltage semiconductor device is provided. Firstly, a substrate is provided, wherein the substrate has a first active zone and a second active zone. Then, a first ion implantation process is performed to dope the substrate by a first mask layer, thereby forming a first-polarity doped region at the two ends of the first active zone and a periphery of the second active zone. After the first mask layer is removed, a second ion implantation process is performed to dope the substrate by a second mask layer, thereby forming a second-polarity doped region at the two ends of the second active zone and a periphery of the first active zone. After the second mask layer is removed, a first gate conductor structure and a second gate conductor structure are formed over the middle segments of the first active zone and the second active zone, respectively.

Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and extending down from the surface of the substrate, and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug penetrating into the isolation and reaching the bottom thereof; and a first doping electrode region having the second conductive type, formed within the second well and below the isolation to connect the conductive plug.

Abstract: The present invention provides a semiconductor device including a substrate, a deep well, a high-voltage well, and a doped region. The substrate and the high-voltage well have a first conductive type, and the deep well and the doped region have a second conductive type different from the first conductive type. The substrate has a high-voltage region and a low-voltage region, and the deep well is disposed in the substrate in the high-voltage region. The high-voltage well is disposed in the substrate between the high-voltage region and the low-voltage region, and the doped region is disposed in the high-voltage well. The doped region and the high-voltage well are electrically connected to a ground.