Patents by Inventor Chih-Chung Yang

Chih-Chung Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240110576
    Abstract: An impeller is provided, including a metal housing, a shaft, and a plastic member. The metal housing has a shaft mounting hole. The inner surface of the shaft mounting hole includes three or more contact points, and the contact points are closer to the shaft than other portions of the inner surface of the shaft mounting hole. The shaft passes through the shaft mounting hole and is affixed by the contact points. The metal housing divides the shaft into an upper section, a middle section, and a lower section. The plastic member passes through the shaft mounting hole and is in contact with the middle section.
    Type: Application
    Filed: December 13, 2023
    Publication date: April 4, 2024
    Inventors: Wei-I LING, Chao-Fu YANG, Chih-Chung CHEN, Kuo-Tung HSU
  • Publication number: 20240099148
    Abstract: A semiconductor device is provided. The semiconductor device includes a memory including a bottom electrode, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and an upper electrode on the MTJ stack. The semiconductor device also includes at least one dielectric layer formed around the memory, wherein a top metal layer contact hole is formed in the at least one dielectric layer, a dielectric liner layer formed in the top metal contact hole, and a top metal layer contact in the top metal layer contact hole.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Inventors: Hsueh-Chung Chen, Koichi Motoyama, Chanro Park, Yann Mignot, Chih-Chao Yang
  • Publication number: 20240096705
    Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
  • Patent number: 10312792
    Abstract: A projection apparatus, a power management apparatus, and a method for power management thereof are provided. The projection apparatus has a first power socket corresponding to a first power specification and a second power socket corresponding to a second power specification. The second power specification is different from the first power specification. A voltage detection unit is adapted to detect an input voltage received by a powered power socket, wherein the powered power socket is the first power socket or the second power socket. A control unit decides whether the input voltage detected by the voltage detection unit is matched up with the power specification of the corresponding powered power socket to determine an operation mode of the projection apparatus and to determine whether the projection apparatus provides an alarm message to ensure safety of use.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: June 4, 2019
    Assignee: Coretronic Corporation
    Inventors: Kuo-Huan Wei, Chih-Chung Yang, Yung-Chuan Tseng, Wen-Chen Chen, Jui-Ming Tsai
  • Patent number: 9820050
    Abstract: A balanced push-pull loudspeaker device includes a loudspeaker box, a first loudspeaker component, a second loudspeaker component and an audio processing unit. The audio processing unit generates a bass audio signal according to low frequency parts of a first audio channel signal and of a second audio channel signal, mixes the bass audio signal and a high frequency part of the first audio channel signal, outputs a mixture of the bass audio signal and the high frequency part of the first audio channel signal to the first loudspeaker component, inverts the bass audio signal, mixes the inverted bass audio signal and a high frequency part of the second audio channel signal, and outputs a mixture of the inverted bass audio signal and the high frequency part of the second audio channel signal to the second loudspeaker component. This disclosure also provides a control method applied to the above loudspeaker device.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: November 14, 2017
    Assignee: AMTRAN TECHNOLOGY CO., LTD.
    Inventors: Chia-Yu Wu, Chih-Chung Yang, Ya-Hsuan Lin
  • Patent number: 9810523
    Abstract: A method for determining if a wire guide roller having a plurality of V-shaped grooves, each having a copper line thereon, arranged column-by-column on a periphery direction thereof is failed after slicing a plurality of wafers is disclosed. Based on the disclosed technical means, the efficacy may be achieved that a damage situation may be automatically examined and notified to maintain a yield in the slicing process in an online high speed environment.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: November 7, 2017
    Assignee: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Yu-Hsuan Lin, Chih-Chung Yang, Kuo-Cheng Huang, Tai-Shan Liao
  • Publication number: 20170265002
    Abstract: A balanced push-pull loudspeaker device includes a loudspeaker box, a first loudspeaker component, a second loudspeaker component and an audio processing unit. The audio processing unit generates a bass audio signal according to low frequency parts of a first audio channel signal and of a second audio channel signal, mixes the bass audio signal and a high frequency part of the first audio channel signal, outputs a mixture of the bass audio signal and the high frequency part of the first audio channel signal to the first loudspeaker component, inverts the bass audio signal, mixes the inverted bass audio signal and a high frequency part of the second audio channel signal, and outputs a mixture of the inverted bass audio signal and the high frequency part of the second audio channel signal to the second loudspeaker component. This disclosure also provides a control method applied to the above loudspeaker device.
    Type: Application
    Filed: January 25, 2017
    Publication date: September 14, 2017
    Applicant: AMTRAN TECHNOLOGY CO.,LTD
    Inventors: Chia-Yu WU, Chih-Chung YANG, Ya-Hsuan LIN
  • Publication number: 20170194851
    Abstract: A projection apparatus, a power management apparatus, and a method for power management thereof are provided. The projection apparatus has a first power socket corresponding to a first power specification and a second power socket corresponding to a second power specification. The second power specification is different from the first power specification. A voltage detection unit is adapted to detect an input voltage received by a powered power socket, wherein the powered power socket is the first power socket or the second power socket. A control unit decides whether the input voltage detected by the voltage detection unit is matched up with the power specification of the corresponding powered power socket to determine an operation mode of the projection apparatus and to determine whether the projection apparatus provides an alarm message to ensure safety of use.
    Type: Application
    Filed: December 28, 2016
    Publication date: July 6, 2017
    Applicant: Coretronic Corporation
    Inventors: Kuo-Huan Wei, Chih-Chung Yang, Yung-Chuan Tseng, Wen-Chen Chen, Jui-Ming Tsai
  • Patent number: 9478701
    Abstract: A semiconductor light-emitting device including a substrate, a first-type doped semiconductor structure, a light-emitting layer, and a second-type doped semiconductor layer is provided. The first-type doped semiconductor structure is located on the substrate and includes a base and multi-section rod structures extended upward from the base. Each multi-section rod structure includes rods and at least one connecting portion. The connecting portion connects adjacent rods along a first direction, wherein the first direction is perpendicular to the base and points to the connecting portion from the base. Cross-section areas of different rods on a reference plane parallel to the substrate are different, and cross-section areas of the connecting portion on the reference plane decrease along the first direction. The light-emitting layer is located on sidewalls of the rods. The second-type doped semiconductor layer is located on the light-emitting layer.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: October 25, 2016
    Assignee: National Taiwan University
    Inventors: Chih-Chung Yang, Che-Hao Liao, Charng-Gan Tu, Horng-Shyang Chen, Chia-Ying Su
  • Publication number: 20160209202
    Abstract: A method for determining if a wire guide roller having a plurality of V-shaped grooves, each having a copper line thereon, arranged column-by-column on a periphery direction thereof is failed after slicing a plurality of wafers is disclosed. Based on the disclosed technical means, the efficacy may be achieved that a damage situation may be automatically examined and notified to maintain a yield in the slicing process in an online high speed environment.
    Type: Application
    Filed: January 21, 2015
    Publication date: July 21, 2016
    Applicant: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Yu-Hsuan LIN, Chih-Chung YANG, Kuo-Cheng HUANG, Tai-Shan LIAO
  • Patent number: 9281184
    Abstract: The invention is directed to a method for forming a nitride on a silicon substrate. In the method of the present invention, a silicon substrate is provided and a buffer layer is formed on the silicon substrate. The formation of the buffer layer includes a multi-level temperature modulation process having a plurality temperature levels and a plurality of temperature modulations. For each of the temperature modulations, the temperature is gradually decreased. A nitride is formed on the buffer layer.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: March 8, 2016
    Assignee: NATIONAL TAIWAN UNIVERSITY
    Inventors: Chih-Chung Yang, Chih-Yen Chen
  • Patent number: 9147805
    Abstract: A semiconductor device including a Si (110) substrate, a buffer layer, a first type doped semiconductor layer, a light-emitting layer and a second type doped semiconductor layer is provided. The Si (110) substrate has a plurality of trenches. Each trench at least extends along a first direction, and the first direction is parallel to a <1-10> crystal direction of the Si (110) substrate. The buffer layer is located on the Si (110) substrate and exposes the trenches. The first type doped semiconductor layer is located on the buffer layer and covers the trenches. The light-emitting layer is located on the first type doped semiconductor layer. The second type doped semiconductor layer is located on the light-emitting layer. A fabrication method of a semiconductor device is also provided.
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: September 29, 2015
    Assignee: National Taiwan University
    Inventors: Chih-Chung Yang, Chun-Han Lin, Chia-Ying Su, Horng-Shyang Chen
  • Publication number: 20150263227
    Abstract: A semiconductor light-emitting device including a substrate, a first-type doped semiconductor structure, a light-emitting layer, and a second-type doped semiconductor layer is provided. The first-type doped semiconductor structure is located on the substrate and includes a base and multi-section rod structures extended upward from the base. Each multi-section rod structure includes rods and at least one connecting portion. The connecting portion connects adjacent rods along a first direction, wherein the first direction is perpendicular to the base and points to the connecting portion from the base. Cross-section areas of different rods on a reference plane parallel to the substrate are different, and cross-section areas of the connecting portion on the reference plane decrease along the first direction. The light-emitting layer is located on sidewalls of the rods. The second-type doped semiconductor layer is located on the light-emitting layer.
    Type: Application
    Filed: April 30, 2014
    Publication date: September 17, 2015
    Applicant: National Taiwan University
    Inventors: Chih-Chung Yang, Che-Hao Liao, Charng-Gan Tu, Horng-Shyang Chen, Chia-Ying Su
  • Publication number: 20150107869
    Abstract: A block for electrical bonding and grounding made by punching and bending a metal sheet is provided. The block for electrical bonding and grounding has a fixing section formed on its bottom end and a connecting section formed uprightly on one side of the fixing section. The fixing section has a ground portion formed thereon by bending a cut portion into a U-shape portion, and the ground portion has a ground wire passage for passing through of a ground wire. The ground wire passage has a shrunk neck portion provided for limiting the ground wire. A threaded hole is provided correspondingly such that a fastening screw can be threaded through the threaded hole to clamp the ground wire securely in position. The overall manufacturing process is easier, more convenient and quicker so that the overall cost is lowered.
    Type: Application
    Filed: October 23, 2014
    Publication date: April 23, 2015
    Inventors: CHIH-PIN YAO, CHUN-YI LI, WEN-LIANG TU, CHIH-CHUNG YANG
  • Publication number: 20150097209
    Abstract: A semiconductor device including a Si (110) substrate, a buffer layer, a first type doped semiconductor layer, a light-emitting layer and a second type doped semiconductor layer is provided. The Si (110) substrate has a plurality of trenches. Each trench at least extends along a first direction, and the first direction is parallel to a <1-10> crystal direction of the Si (110) substrate. The buffer layer is located on the Si (110) substrate and exposes the trenches. The first type doped semiconductor layer is located on the buffer layer and covers the trenches. The light-emitting layer is located on the first type doped semiconductor layer. The second type doped semiconductor layer is located on the light-emitting layer. A fabrication method of a semiconductor device is also provided.
    Type: Application
    Filed: November 29, 2013
    Publication date: April 9, 2015
    Applicant: National Taiwan University
    Inventors: Chih-Chung Yang, Chun-Han Lin, Chia-Ying Su, Horng-Shyang Chen
  • Patent number: 8886996
    Abstract: A debugging device for performing a debugging process through an electronic device external connector system is provided. The debugging device performs the debugging process to a target system, and the device comprises a first external connector, a switch, and a debugging module. The first external connector is connected to the external port of the target system. The switch is connected to the first external connector, and the switch chooses to activate the debugging process. The debugging module is connected to the switch, and the debugging module receives a universal asynchronous receiver/transmitter (UART) signal provided by the target system.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: November 11, 2014
    Assignee: Compal Electronics, Inc.
    Inventors: Chih-Chung Yang, Chun-Sheng Chen, Hsin-Hung Shen
  • Patent number: 8759814
    Abstract: A semiconductor light-emitting device and a manufacturing method thereof are provided, wherein the semiconductor light-emitting device includes a first type doped semiconductor structure, a light-emitting layer, a second type doped semiconductor layer, a first conductive layer and a dielectric layer. The first type doped semiconductor structure includes a base and a plurality of columns extending outward from the base. Each of the columns includes a top surface and a plurality of sidewall surfaces. The light-emitting layer is disposed on the sidewall surfaces and the top surface, wherein the surface area of the light-emitting layer gradually changes from one side adjacent to the columns to a side away from the columns. The dielectric layer exposes the first conductive layer locating on the top surface of each of the columns, wherein the dielectric layer includes at least one of a plurality of quantum dots, phosphors, and metal nanoparticles.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 24, 2014
    Assignee: National Taiwan University
    Inventors: Chih-Chung Yang, Che-Hao Liao, Shao-Ying Ting, Horng-Shyang Chen, Wen-Ming Chang, Yu-Feng Yao, Chih-Yen Chen, Hao-Tsung Chen
  • Patent number: 8753559
    Abstract: A fabrication method of nanoparticles is provided. A substrate having a plurality of pillar structures is provided and then a plurality of ring structures is formed to surround the plurality of the pillar structures. The inner wall of each ring structure surrounds the sidewall of each pillar structure. A portion of each pillar structure is removed to reduce the height of each pillar structure and to expose the inner wall of each ring structure. The ring structures are separated from the pillar structures to form a plurality of nanoparticles. Surface modifications are applied to the ring structures before the ring structures are separated from the pillar structures on the substrate.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: June 17, 2014
    Assignee: National Taiwan University
    Inventors: Chih-Chung Yang, Hung-Yu Tseng, Wei-Fang Chen, Che-Hao Liao, Yu-Feng Yao
  • Patent number: 8724877
    Abstract: A mirror image suppression method adapted to an optical coherence tomography (OCT) system is provided. The mirror image suppression method includes the following steps: obtaining a tomography image of an object to be tested by using the OCT system; calculating one real image signal obtained from an nth specific-mode scan for a specific pixel of the tomography image based on image signals obtained from an (n?1)th and the nth specific-mode scans; obtaining one real image signal of each of a plurality of pixels in the tomography image based on the calculation in the step of calculating the one real image signal; and reconstructing the tomography image based on the real image signal of each of the pixels obtained in the step of obtaining the one real image signal to suppress mirror image signals of the tomography image.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: May 13, 2014
    Assignee: National Taiwan University
    Inventors: Chih-Chung Yang, Chiung-Ting Wu, Cheng-Kuang Lee, Ting-Ta Chi
  • Publication number: 20140042387
    Abstract: A semiconductor light-emitting device and a manufacturing method thereof are provided, wherein the semiconductor light-emitting device includes a first type doped semiconductor structure, a light-emitting layer, a second type doped semiconductor layer, a first conductive layer and a dielectric layer. The first type doped semiconductor structure includes a base and a plurality of columns extending outward from the base. Each of the columns includes a top surface and a plurality of sidewall surfaces. The light-emitting layer is disposed on the sidewall surfaces and the top surface, wherein the surface area of the light-emitting layer gradually changes from one side adjacent to the columns to a side away from the columns. The dielectric layer exposes the first conductive layer locating on the top surface of each of the columns, wherein the dielectric layer includes at least one of a plurality of quantum dots, phosphors, and metal nanoparticles.
    Type: Application
    Filed: September 13, 2012
    Publication date: February 13, 2014
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: Chih-Chung Yang, Che-Hao Liao, Shao-Ying Ting, Horng-Shyang Chen, Wen-Ming Chang, Yu-Feng Yao, Chih-Yen Chen, Hao-Tsung Chen