Patents by Inventor Chih Fang
Chih Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240147401Abstract: An association management method includes: after coordination association between a client and a plurality of member APs in a multi-access point (MAP) system is successfully completed, generating a request frame to manage association between the client and a member AP in the MAP system. For example, the request frame may be initiated by the client. For another example, the request frame may be initiated by the member AP.Type: ApplicationFiled: October 3, 2023Publication date: May 2, 2024Applicant: MEDIATEK INC.Inventors: Chien-Fang Hsu, Chih-Chun Kuo
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Patent number: 11964811Abstract: A liquid storage tank includes a housing, a piston located in the housing, a cover, an elastic element, and an outlet pipe. The cover is attached to the housing and has a support post extending toward the piston. The piston, the housing, and the cover define a tank chamber. The tank chamber is filled with cooling liquid. The elastic element is connected with the tank hosing and the piston. The elastic element is free from contact with the cooling liquid. The outlet pipe communicates with the tank chamber. An extension direction of an opening of the outlet pipe is not parallel to a direction of movement of the elastic element. When the cooling liquid is decreased, the piston compressed the tank chamber such that the elastic element is released. The tank chamber is continuously compressed by pairing the elastic element and the piston.Type: GrantFiled: June 21, 2022Date of Patent: April 23, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Yu-Jei Huang, Wei-Fang Wu, Chia-Ying Hsu, Chih-Chieh Lu
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Publication number: 20240128531Abstract: The present disclosure discloses a method for recycling all types of lithium batteries. First, the lithium battery waste is acid-leached to obtain a solution containing most of metal ions. After filtering, the solution is separated from the remaining solids, and then the obtained solution is subjected to separate precipitation many times. After separately adjusting the pH value of the solution many times, adding precipitants with a high selectivity ratio, and matching with filtration and separation reaction, all ions in the lithium battery waste are sequentially precipitated in forms of iron phosphate (FePO4), aluminum hydroxide (Al(OH)3), manganese oxide (MnO2), dicobalt trioxide (cobalt oxide, Co2O3), nickel hydroxide (Ni(OH)2), and lithium carbonate (Li2CO3).Type: ApplicationFiled: September 24, 2023Publication date: April 18, 2024Applicant: Cleanaway Company LimitedInventors: CHIH-HUANG LAI, HSIN-FANG CHANG, TZU-MIN CHENG, YUNG-FA YANG, TSUNG-TIEN CHEN, ZHENG-YU CHENG, CHI-YUNG CHANG
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Patent number: 11954453Abstract: Systems and methods for natural language generation by an edge computing device are disclosed. In one embodiments, a method comprises: receiving, by an edge computing device, event data from an edge event; determining, by the edge computing device, that a network connection to a cloud server is not available; extracting, by the edge computing device, features of the event data; predicting, by a local neural network of the edge computing device, an action for the edge computing device to take based on the features of the event data, wherein the action is associated with a confidence level; and determining, by the edge computing device, whether the confidence level meets a predetermined threshold value.Type: GrantFiled: March 12, 2019Date of Patent: April 9, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chih-Hsiung Liu, I-Chien Lin, Cheng-Fang Lin, Joey H. Y. Tseng
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Patent number: 11950016Abstract: The present invention provides a control method of a receiver. The control method includes the steps of: when the receiver enters a sleep/standby mode, continually detecting an auxiliary signal from an auxiliary channel to generate a detection result; and if the detection result indicates that the auxiliary signal has a preamble or a specific pattern, generating a wake-up control signal to wake up the receiver before successfully receiving the auxiliary signal having a wake-up command.Type: GrantFiled: April 15, 2020Date of Patent: April 2, 2024Assignee: MEDIATEK INC.Inventors: Chun-Chia Chen, Chih-Hung Pan, Chia-Chi Liu, Shun-Fang Liu, Meng-Kun Li, Chao-An Chen
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Patent number: 11943077Abstract: A multidrop network system includes N network devices. The N network devices include a master device and multiple slave devices, and each network device has an identification code as its own identification in the multidrop network system. The N network devices have N identification codes and obtain transmission opportunities in turn according to the N identification codes in each round of data transmission. Each network device performs a count operation to generate a current count value, and when the identification code of a network device is the same as the current count value, this network device obtains a transmission opportunity. After a device obtains the transmission opportunity, it determines whether a cut-in signal from another network device is observed in a front duration of a predetermined time slot, and then determines whether to abandon/defer the right to start transmitting in the remaining duration of the predetermined time slot.Type: GrantFiled: May 31, 2022Date of Patent: March 26, 2024Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Yung-Le Chang, Wen-Chih Fang, Deng-Shian Wang, Shieh-Hsing Kuo
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Publication number: 20240096622Abstract: An embodiment etching tool includes an etch chamber for plasma etching a first wafer to be processed; a transfer chamber coupled to the etch chamber; a first run path between the transfer chamber and the etch chamber, the first run path including a path for moving the first wafer to be processed from the transfer chamber to the etch chamber, where the etching tool is configured to dry develop the first wafer to be processed before etching a hard mask on the first wafer in the etch chamber.Type: ApplicationFiled: September 21, 2022Publication date: March 21, 2024Inventors: Steven Grzeskowiak, Eric Chih-Fang Liu
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Publication number: 20240094282Abstract: A circuit test structure includes a chip including a conductive line which traces a perimeter of the chip. The circuit test structure further includes an interposer electrically connected to the chip, wherein the conductive line is over both the chip and the interposer. The circuit test structure further includes a test structure connected to the conductive line. The circuit test structure further includes a testing site, wherein the test structure is configured to electrically connect the testing site to the conductive line.Type: ApplicationFiled: November 22, 2023Publication date: March 21, 2024Inventors: Ching-Fang CHEN, Hsiang-Tai LU, Chih-Hsien LIN
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Publication number: 20240087892Abstract: A method of forming a semiconductor device includes forming, over a hardmask layer and an underlying layer of a substrate, a pattern of first trenches between adjacent template lines, each of the first trenches exposing a portion of the hardmask layer, and each of the template lines including a mandrel and spacers on sidewalls of the mandrel; forming a pattern of first blocks over the pattern of the first trenches and the template lines, the first blocks dividing the first trenches to form a pattern of first stencil trenches; transferring the pattern of first stencil trenches to the hardmask layer to form a pattern of first hardmask trenches, each of the first hardmask trenches exposing a portion of the underlying layer; forming a first fill layer filling the first hardmask trenches and exposing the mandrels; selectively removing the mandrels to form second trenches, each of the second trenches exposing a portion of the hardmask layer; and forming a conformal liner in the second trenches and over a surface ofType: ApplicationFiled: September 9, 2022Publication date: March 14, 2024Inventors: Eric Chih-Fang Liu, Katie Lutker-Lee, Steven Grzeskowiak, Jodi Grzeskowiak, Jeffrey Smith, David L. O'Meara
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Publication number: 20240087907Abstract: The present disclosure combines chemical mechanical polishing (CMP), wet etch and deposition processes to provide improved processes and methods for planarizing an uneven surface of a material layer deposited over a plurality of structures formed on a substrate. A CMP process is initially used to smooth the uneven surface and provide complete local planarization of the material layer above the plurality of structures. After achieving complete local planarization, a wet etch process is used to etch the material layer until a uniform recess is formed between the plurality of structures and the material layer is provided with a uniform thickness across the substrate. In some embodiments, an additional material layer may be deposited and a second CMP process may be used to planarize the additional material layer to provide the substrate with a globally planarized surface.Type: ApplicationFiled: September 12, 2022Publication date: March 14, 2024Inventors: Shan Hu, Eric Chih-Fang Liu, Henan Zhang, Sangita Kumari, Peter Delia
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Publication number: 20240087891Abstract: A method of patterning a substrate includes forming a first line, a second line, and a third line over the substrate, the first line, the second line, and the third line being parallel in a plan view, and forming a fourth line and a fifth line over the first line, the second line, and the third line, the fourth line and the fifth line being orthogonal to the first line in the plan view. The method further includes etching a hole through the second line using the first line, the third line, the fourth line, and the fifth line as an etching mask, and filling the hole with a dielectric material to form a block.Type: ApplicationFiled: September 13, 2022Publication date: March 14, 2024Inventors: Eric Chih-Fang Liu, Shihsheng Chang, Kai-Hung Yu, Yun Han
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Publication number: 20240087950Abstract: Embodiments of improved process flows and methods are provided in the present disclosure to form air gaps between metal interconnects. More specifically, the present disclosure provides improved process flows and methods that utilize a wet etch process to form recesses between metal interconnects formed on a patterned substrate. Unlike conventional air gap integration methods, the improved process flows and methods described herein utilize the critical dimension (CD) dependent etching provided by wet etch processes to etch an intermetal dielectric material formed between the metal interconnects at a faster rate than the intermetal dielectric material is etched in surrounding areas of the patterned substrate. This enables the improved process flows and methods described herein to form recesses (and subsequently form air gaps) between the metal interconnects without using a dry etch process.Type: ApplicationFiled: September 12, 2022Publication date: March 14, 2024Inventors: Shan Hu, Eric Chih-Fang Liu, Henan Zhang, Sangita Kumari, Peter Delia
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Publication number: 20240087909Abstract: Embodiments of improved process flows and methods are provided in the present disclosure to control fin height and channel area in a fin field effect transistor (FinFET) having gaps of variable CD. More specifically, the present disclosure provides improved transistor fabrication processes and methods that utilize a wet etch process, instead of a dry etch process, to remove the oxide material deposited within the gaps formed between the fins of a FinFET. By utilizing a wet etch process, the improved transistor fabrication processes and methods described herein provide a means to adjust or individually control the fin height of one or more the fins, thereby providing greater control over the channel area of the FinFET.Type: ApplicationFiled: September 12, 2022Publication date: March 14, 2024Inventors: Shan Hu, Eric Chih-Fang Liu, Henan Zhang, Sangita Kumari, Peter Delia
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Publication number: 20240063019Abstract: A method of forming a semiconductor device, where the method includes receiving a substrate in a processing chamber, the substrate including a first patterned layer including a metal-based material; and with a gaseous etch process, trimming the first patterned layer to form a second patterned layer, the gaseous etch process including exposing the first patterned layer to an un-ionized gas including a halogen compound.Type: ApplicationFiled: August 16, 2022Publication date: February 22, 2024Inventors: Alexandra Krawicz, Steven Grzeskowiak, Eric Chih-Fang Liu
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Patent number: 11900150Abstract: A system and method for storing data associated with a system management interrupt (SMI) in a computer system. Notification of a system management interrupt is received on a central processing unit. The central processing unit enters a system management mode. A system management handler of a basic input output system (BIOS) is executed by a bootstrap processor of the central processing unit. The system management interrupt is initiated via the bootstrap processor. The system management interrupt data is stored in a register of the bootstrap processor. The SMI data is converted to an accessible format. The converted SMI data is stored in a memory.Type: GrantFiled: December 29, 2021Date of Patent: February 13, 2024Assignee: QUANTA COMPUTER INC.Inventors: Chih-Hsiang Hsu, Wei-Wei Li, Shang-Lin Tsai, Lueh-Chih Fang
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Publication number: 20240047210Abstract: A method of processing a substrate that includes: forming recesses in a first mask layer over a mask stack including a lower hardmask, a middle mask, and an upper hardmask, the recesses defining an initial pattern including a plurality of spacer structures, each of the spacer structures having a first sidewall and an opposite second sidewall, the first sidewall having a different height from the second sidewall; etching the upper hardmask, selectively to the middle mask, to transfer the initial pattern to the upper hardmask; etching the middle mask, selectively to the lower hardmask and the patterned upper hardmask, to transfer a pattern of the patterned upper hardmask to the middle mask; and etching the lower hardmask, selectively to the patterned middle mask, to transfer a pattern of the patterned middle mask to the lower hardmask.Type: ApplicationFiled: August 3, 2022Publication date: February 8, 2024Inventors: Eric Chih-Fang Liu, Christopher Cole, Steven Grzeskowiak, Katie Lutker-Lee, Xinghua Sun, Daniel Santos Rivera
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Patent number: 11887967Abstract: A semiconductor device package includes a substrate, a connection structure, a first package body and a first electronic component. The substrate has a first surface and a second surface opposite to the first surface. The connection structure is disposed on the firs surface of the substrate. The first package body is disposed on the first surface of the substrate. The first package body covers the connection structure and exposes a portion of the connection structure. The first electronic component is disposed on the first package body and in contact with the portion of the connection structure exposed by the first package body.Type: GrantFiled: October 4, 2021Date of Patent: January 30, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Shang-Ruei Wu, Chien-Yuan Tseng, Meng-Jen Wang, Chen-Tsung Chang, Chih-Fang Wang, Cheng-Han Li, Chien-Hao Chen, An-Chi Tsao, Per-Ju Chao
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Patent number: 11888755Abstract: A multidrop network system includes N network devices. The N network devices includes M transmission-permissible devices including a master device and at least one slave device, wherein M is not greater than N. Each transmission-permissible device has at least one identification code as its identification in the multidrop network system, and the M transmission-permissible devices have at least N identification codes. The M transmission-permissible devices obtain transmission opportunities in turn according to their respective identification codes in each round of data transmission. A Kth device among the M transmission-permissible devices has multiple identification codes, and thus obtains multiple transmission opportunities in one round of data transmission.Type: GrantFiled: July 19, 2022Date of Patent: January 30, 2024Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Yung-Le Chang, Wen-Chih Fang, Deng-Shian Wang, Shieh-Hsing Kuo
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Publication number: 20230372746Abstract: A face mask apparatus is provided for protecting the user from viruses, bacteria, dust, etc. The face mask apparatus includes a base mask, a gas supply pump and a connecting tube. The base mask includes a shielding surface, a breathing chamber and a pair of ear straps. By virtue of pumping the air into the sealed base mask with the external gas supply pump for inhalation and expelling the excess air through a plurality of air passageway, the face mask apparatus of the present disclosure shields infiltration of the external viruses and bacteria from the slit of the mask.Type: ApplicationFiled: May 23, 2022Publication date: November 23, 2023Inventor: CHIH-FANG LO
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Patent number: 11810974Abstract: A semiconductor structure includes: a U-metal-oxide-semiconductor field-effect transistor (UMOS) structure; and a trench junction barrier Schottky (TJBS) diode, wherein an insulating layer of a sidewall of the TJBS diode does not have a side gate.Type: GrantFiled: June 25, 2021Date of Patent: November 7, 2023Assignee: NATIONAL TSING HUA UNIVERSITYInventors: Chih-Fang Huang, Jia-Wei Hu, You-An Lin, Yong-Shiang Jan