Abstract: A method of forming a semiconductor device includes forming, over a hardmask layer and an underlying layer of a substrate, a pattern of first trenches between adjacent template lines, each of the first trenches exposing a portion of the hardmask layer, and each of the template lines including a mandrel and spacers on sidewalls of the mandrel; forming a pattern of first blocks over the pattern of the first trenches and the template lines, the first blocks dividing the first trenches to form a pattern of first stencil trenches; transferring the pattern of first stencil trenches to the hardmask layer to form a pattern of first hardmask trenches, each of the first hardmask trenches exposing a portion of the underlying layer; forming a first fill layer filling the first hardmask trenches and exposing the mandrels; selectively removing the mandrels to form second trenches, each of the second trenches exposing a portion of the hardmask layer; and forming a conformal liner in the second trenches and over a surface of

Abstract: Embodiments of improved process flows and methods are provided in the present disclosure to control fin height and channel area in a fin field effect transistor (FinFET) having gaps of variable CD. More specifically, the present disclosure provides improved transistor fabrication processes and methods that utilize a wet etch process, instead of a dry etch process, to remove the oxide material deposited within the gaps formed between the fins of a FinFET. By utilizing a wet etch process, the improved transistor fabrication processes and methods described herein provide a means to adjust or individually control the fin height of one or more the fins, thereby providing greater control over the channel area of the FinFET.

Abstract: A method of patterning a substrate includes forming a first line, a second line, and a third line over the substrate, the first line, the second line, and the third line being parallel in a plan view, and forming a fourth line and a fifth line over the first line, the second line, and the third line, the fourth line and the fifth line being orthogonal to the first line in the plan view. The method further includes etching a hole through the second line using the first line, the third line, the fourth line, and the fifth line as an etching mask, and filling the hole with a dielectric material to form a block.

Abstract: The present disclosure combines chemical mechanical polishing (CMP), wet etch and deposition processes to provide improved processes and methods for planarizing an uneven surface of a material layer deposited over a plurality of structures formed on a substrate. A CMP process is initially used to smooth the uneven surface and provide complete local planarization of the material layer above the plurality of structures. After achieving complete local planarization, a wet etch process is used to etch the material layer until a uniform recess is formed between the plurality of structures and the material layer is provided with a uniform thickness across the substrate. In some embodiments, an additional material layer may be deposited and a second CMP process may be used to planarize the additional material layer to provide the substrate with a globally planarized surface.

Abstract: A method of forming a semiconductor device, where the method includes receiving a substrate in a processing chamber, the substrate including a first patterned layer including a metal-based material; and with a gaseous etch process, trimming the first patterned layer to form a second patterned layer, the gaseous etch process including exposing the first patterned layer to an un-ionized gas including a halogen compound.

Abstract: A system and method for storing data associated with a system management interrupt (SMI) in a computer system. Notification of a system management interrupt is received on a central processing unit. The central processing unit enters a system management mode. A system management handler of a basic input output system (BIOS) is executed by a bootstrap processor of the central processing unit. The system management interrupt is initiated via the bootstrap processor. The system management interrupt data is stored in a register of the bootstrap processor. The SMI data is converted to an accessible format. The converted SMI data is stored in a memory.

Abstract: A method of processing a substrate that includes: forming recesses in a first mask layer over a mask stack including a lower hardmask, a middle mask, and an upper hardmask, the recesses defining an initial pattern including a plurality of spacer structures, each of the spacer structures having a first sidewall and an opposite second sidewall, the first sidewall having a different height from the second sidewall; etching the upper hardmask, selectively to the middle mask, to transfer the initial pattern to the upper hardmask; etching the middle mask, selectively to the lower hardmask and the patterned upper hardmask, to transfer a pattern of the patterned upper hardmask to the middle mask; and etching the lower hardmask, selectively to the patterned middle mask, to transfer a pattern of the patterned middle mask to the lower hardmask.

Abstract: A multidrop network system includes N network devices. The N network devices includes M transmission-permissible devices including a master device and at least one slave device, wherein M is not greater than N. Each transmission-permissible device has at least one identification code as its identification in the multidrop network system, and the M transmission-permissible devices have at least N identification codes. The M transmission-permissible devices obtain transmission opportunities in turn according to their respective identification codes in each round of data transmission. A Kth device among the M transmission-permissible devices has multiple identification codes, and thus obtains multiple transmission opportunities in one round of data transmission.

Abstract: A semiconductor device package includes a substrate, a connection structure, a first package body and a first electronic component. The substrate has a first surface and a second surface opposite to the first surface. The connection structure is disposed on the firs surface of the substrate. The first package body is disposed on the first surface of the substrate. The first package body covers the connection structure and exposes a portion of the connection structure. The first electronic component is disposed on the first package body and in contact with the portion of the connection structure exposed by the first package body.

Abstract: A face mask apparatus is provided for protecting the user from viruses, bacteria, dust, etc. The face mask apparatus includes a base mask, a gas supply pump and a connecting tube. The base mask includes a shielding surface, a breathing chamber and a pair of ear straps. By virtue of pumping the air into the sealed base mask with the external gas supply pump for inhalation and expelling the excess air through a plurality of air passageway, the face mask apparatus of the present disclosure shields infiltration of the external viruses and bacteria from the slit of the mask.

Abstract: A semiconductor structure includes: a U-metal-oxide-semiconductor field-effect transistor (UMOS) structure; and a trench junction barrier Schottky (TJBS) diode, wherein an insulating layer of a sidewall of the TJBS diode does not have a side gate.

Abstract: A process includes forming, over a dielectric layer, a hardmask stack including a first layer below a second layer below a third layer below a fourth layer. The first and third layers include a different hardmask material from the second and fourth layers. A trench pattern including sidewall spacer structures is formed over the hardmask stack. The fourth layer is etched in a first region. The fourth and third layers are etched in a second region. The fourth and third layers are etched in a third region. The fourth layer is etched in a fourth region. The second and first layers are etched in the second and third regions. The third layer is etched in the first and fourth regions. In the dielectric layer, trenches are formed in the first and fourth regions, and via openings, deeper than the trenches, are formed in the second and third regions.

Abstract: Various embodiments of stacked structures, process steps and methods are provided herein for etching high aspect ratio features (e.g., contact holes, vias, trenches, etc.) within a stacked structure comprising a hard mask layer, which is formed above and in contact with one or more underlying layers. At least one etch stop layer (ESL) is provided within the hard mask layer to divide the hard mask layer into two or more distinct portions. When the stacked structure is subsequently etched to form high aspect ratio features within the hard mask layer, such as contact holes or vias that extend through the hard mask layer, the ESL(s) included within the hard mask layer improve etch rate and critical dimension (CD) uniformity of the features etched within the hard mask layer.

Abstract: The present disclosure provides various embodiments of plasma processing systems, plasma etch process steps and methods for etching features (e.g., contact holes, vias, trenches, etc.) within one or more material layers formed on a substrate, where such material layers include but are not limited to, a metal hard mask layer formed above a dielectric layer. The embodiments disclosed herein reduce or eliminate problems, such as undercutting of the metal hard mask layer and/or recess into the underlying dielectric layer, that occur during conventional continuous wave plasma etch processes by using a pulsed plasma to etch the features within the metal hard mask layer. A radio frequency (RF) modulated pulsed plasma scheme is disclosed herein to improve anisotropic etching of the features within the metal hard mask layer.

Abstract: A method of fabricating an amorphous carbon layer (ACL) mask includes forming an ACL on an underlying layer. The ACL includes a soft ACL portion that has a first hardness and a hard ACL portion that has a second hardness. The soft ACL portion underlies the hard ACL portion. The second hardness is greater than the first hardness. The method further includes forming a patterned layer over the ACL and forming an ACL mask by etching through both the soft ACL portion and the hard ACL portion of the ACL to expose the underlying layer using the patterned layer as an etch mask. Forming the ACL may include depositing one or both of the soft ACL portion and the hard ACL portion. Processing conditions may also be varied while forming the ACL to create a hardness gradient that transitions from softer to harder.

Abstract: A network device including a main bridge, a first bridge, a controller, and an Ethernet port is provided. When the Ethernet port is connected to a mesh network, the processing unit performs the following steps: controlling the Ethernet port to transmit a first broadcast packet; when the Ethernet port receives a second broadcast packet, parsing the second broadcast packet to extract the packet path information to determine whether a path loop exists; determining, according to the Ethernet interface weight (EIW), the slave interface uplink weight (SIUW), and the master device weight (MW) carried by the first broadcast packet and the second broadcast packet, (1) whether the network device plays a master device role, (2) whether the bridge of the Ethernet port is set as the main bridge or the first bridge, and (3) whether the Ethernet port allows data transmission.

Abstract: A method is described for patterning a dielectric layer disposed over a semiconductor substrate layer. The patterning process includes forming a patterned hard mask layer over the dielectric layer, the patterned hard mask layer exposing a portion of a major surface of the dielectric layer. A portion of the dielectric layer is removed by a cyclic etch process, where performing one cycle of the cyclic etch process comprises forming a capping layer selectively over the patterned hard mask layer and performing a timed etch process that removes material from the dielectric layer. In another method, the deposition over the hard mask and the removal of the portion of the dielectric layer are performed concurrently.

Abstract: A semiconductor structure includes a Schottky diode structure, which includes: a first trench extending through a first N-type semiconductor layer and being disposed in the first N-type semiconductor layer; a first insulating layer disposed in the first trench; two polysilicon layers or metal silicide layers disposed in the first trench, wherein an upper one and a lower one of the polysilicon layers or metal silicide layers are disposed in parallel; a first P-type protective layer, which is grounded and disposed on a bottom of the first trench, and contacts the first insulating layer and a bottom surface of the lower one of the polysilicon layers or metal silicide layers; a metal layer respectively disposed as a top surface and a lower bottom surface of the semiconductor structure to form a source and a drain as electrodes for the semiconductor structure to be connected to an external device.

Abstract: A system and method for storing data associated with a system management interrupt (SMI) in a computer system. Notification of a system management interrupt is received on a central processing unit. The central processing unit enters a system management mode. A system management handler of a basic input output system (BIOS) is executed by a bootstrap processor of the central processing unit. The system management interrupt is initiated via the bootstrap processor. The system management interrupt data is stored in a register of the bootstrap processor. The SMI data is converted to an accessible format. The converted SMI data is stored in a memory.

Abstract: Methods are provided herein for forming spacers on a patterned substrate. A self-aligned multiple patterning (SAMP) process is utilized for patterning structures, spacers formed adjacent mandrels, on a substrate. In one embodiment, a novel approach of etching titanium oxide (TiO2) spacers is provided. Highly anisotropic etching of the spacer along with a selective top deposition is provided. In one embodiment, an inductively coupled plasma (ICP) etch tool is utilized. The etching process may be achieved as a one-step etching process. More particularly, a protective layer may be selectively formed on the top of the spacer to protect the mandrel as well as minimize the difference of the etching rates of the spacer top and the spacer bottom. In one embodiment, the techniques may be utilized to etch TiO2 spacers formed along amorphous silicon mandrels using an ICP etch tool utilizing a one-step etch process.