Patents by Inventor Chih Fang

Chih Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11888755
    Abstract: A multidrop network system includes N network devices. The N network devices includes M transmission-permissible devices including a master device and at least one slave device, wherein M is not greater than N. Each transmission-permissible device has at least one identification code as its identification in the multidrop network system, and the M transmission-permissible devices have at least N identification codes. The M transmission-permissible devices obtain transmission opportunities in turn according to their respective identification codes in each round of data transmission. A Kth device among the M transmission-permissible devices has multiple identification codes, and thus obtains multiple transmission opportunities in one round of data transmission.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: January 30, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yung-Le Chang, Wen-Chih Fang, Deng-Shian Wang, Shieh-Hsing Kuo
  • Publication number: 20230372746
    Abstract: A face mask apparatus is provided for protecting the user from viruses, bacteria, dust, etc. The face mask apparatus includes a base mask, a gas supply pump and a connecting tube. The base mask includes a shielding surface, a breathing chamber and a pair of ear straps. By virtue of pumping the air into the sealed base mask with the external gas supply pump for inhalation and expelling the excess air through a plurality of air passageway, the face mask apparatus of the present disclosure shields infiltration of the external viruses and bacteria from the slit of the mask.
    Type: Application
    Filed: May 23, 2022
    Publication date: November 23, 2023
    Inventor: CHIH-FANG LO
  • Patent number: 11810974
    Abstract: A semiconductor structure includes: a U-metal-oxide-semiconductor field-effect transistor (UMOS) structure; and a trench junction barrier Schottky (TJBS) diode, wherein an insulating layer of a sidewall of the TJBS diode does not have a side gate.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: November 7, 2023
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Chih-Fang Huang, Jia-Wei Hu, You-An Lin, Yong-Shiang Jan
  • Publication number: 20230352343
    Abstract: A process includes forming, over a dielectric layer, a hardmask stack including a first layer below a second layer below a third layer below a fourth layer. The first and third layers include a different hardmask material from the second and fourth layers. A trench pattern including sidewall spacer structures is formed over the hardmask stack. The fourth layer is etched in a first region. The fourth and third layers are etched in a second region. The fourth and third layers are etched in a third region. The fourth layer is etched in a fourth region. The second and first layers are etched in the second and third regions. The third layer is etched in the first and fourth regions. In the dielectric layer, trenches are formed in the first and fourth regions, and via openings, deeper than the trenches, are formed in the second and third regions.
    Type: Application
    Filed: April 27, 2023
    Publication date: November 2, 2023
    Applicant: Tokyo Electron Limited
    Inventors: Jeffrey SMITH, David POWER, Eric Chih-Fang LIU, Anton J. DEVILLIERS, Kandabara TAPILY, Jodi GRZESKOWIAK, David CONKLIN, Michael MURPHY
  • Publication number: 20230343598
    Abstract: Various embodiments of stacked structures, process steps and methods are provided herein for etching high aspect ratio features (e.g., contact holes, vias, trenches, etc.) within a stacked structure comprising a hard mask layer, which is formed above and in contact with one or more underlying layers. At least one etch stop layer (ESL) is provided within the hard mask layer to divide the hard mask layer into two or more distinct portions. When the stacked structure is subsequently etched to form high aspect ratio features within the hard mask layer, such as contact holes or vias that extend through the hard mask layer, the ESL(s) included within the hard mask layer improve etch rate and critical dimension (CD) uniformity of the features etched within the hard mask layer.
    Type: Application
    Filed: April 22, 2022
    Publication date: October 26, 2023
    Inventors: Shihsheng Chang, Andrew Metz, Yun Han, Minjoon Park, Kai-Hung Yu, Eric Chih-Fang Liu
  • Publication number: 20230343554
    Abstract: The present disclosure provides various embodiments of plasma processing systems, plasma etch process steps and methods for etching features (e.g., contact holes, vias, trenches, etc.) within one or more material layers formed on a substrate, where such material layers include but are not limited to, a metal hard mask layer formed above a dielectric layer. The embodiments disclosed herein reduce or eliminate problems, such as undercutting of the metal hard mask layer and/or recess into the underlying dielectric layer, that occur during conventional continuous wave plasma etch processes by using a pulsed plasma to etch the features within the metal hard mask layer. A radio frequency (RF) modulated pulsed plasma scheme is disclosed herein to improve anisotropic etching of the features within the metal hard mask layer.
    Type: Application
    Filed: April 20, 2022
    Publication date: October 26, 2023
    Inventors: Ya-Ming Chen, Eric Chih-Fang Liu, Shihsheng Chang, Emilia Hirsch, Na Young Bae, Angelique Raley
  • Publication number: 20230343592
    Abstract: A method of fabricating an amorphous carbon layer (ACL) mask includes forming an ACL on an underlying layer. The ACL includes a soft ACL portion that has a first hardness and a hard ACL portion that has a second hardness. The soft ACL portion underlies the hard ACL portion. The second hardness is greater than the first hardness. The method further includes forming a patterned layer over the ACL and forming an ACL mask by etching through both the soft ACL portion and the hard ACL portion of the ACL to expose the underlying layer using the patterned layer as an etch mask. Forming the ACL may include depositing one or both of the soft ACL portion and the hard ACL portion. Processing conditions may also be varied while forming the ACL to create a hardness gradient that transitions from softer to harder.
    Type: Application
    Filed: April 21, 2022
    Publication date: October 26, 2023
    Inventors: Shihsheng Chang, Andrew Metz, Yun Han, Ya-Ming Chen, Kai-Hung Yu, Eric Chih-Fang Liu
  • Patent number: 11765606
    Abstract: A network device including a main bridge, a first bridge, a controller, and an Ethernet port is provided. When the Ethernet port is connected to a mesh network, the processing unit performs the following steps: controlling the Ethernet port to transmit a first broadcast packet; when the Ethernet port receives a second broadcast packet, parsing the second broadcast packet to extract the packet path information to determine whether a path loop exists; determining, according to the Ethernet interface weight (EIW), the slave interface uplink weight (SIUW), and the master device weight (MW) carried by the first broadcast packet and the second broadcast packet, (1) whether the network device plays a master device role, (2) whether the bridge of the Ethernet port is set as the main bridge or the first bridge, and (3) whether the Ethernet port allows data transmission.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: September 19, 2023
    Assignee: ARCADYAN TECHNOLOGY CORPORATION
    Inventors: Kuo-Shu Huang, Tsung-Hsien Hsieh, Chih-Fang Lee
  • Patent number: 11756790
    Abstract: A method is described for patterning a dielectric layer disposed over a semiconductor substrate layer. The patterning process includes forming a patterned hard mask layer over the dielectric layer, the patterned hard mask layer exposing a portion of a major surface of the dielectric layer. A portion of the dielectric layer is removed by a cyclic etch process, where performing one cycle of the cyclic etch process comprises forming a capping layer selectively over the patterned hard mask layer and performing a timed etch process that removes material from the dielectric layer. In another method, the deposition over the hard mask and the removal of the portion of the dielectric layer are performed concurrently.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: September 12, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Yen-Tien Lu, Xinghua Sun, Shihsheng Chang, Eric Chih-Fang Liu, Angelique Raley, Katie Lutker-Lee
  • Publication number: 20230275161
    Abstract: A semiconductor structure includes a Schottky diode structure, which includes: a first trench extending through a first N-type semiconductor layer and being disposed in the first N-type semiconductor layer; a first insulating layer disposed in the first trench; two polysilicon layers or metal silicide layers disposed in the first trench, wherein an upper one and a lower one of the polysilicon layers or metal silicide layers are disposed in parallel; a first P-type protective layer, which is grounded and disposed on a bottom of the first trench, and contacts the first insulating layer and a bottom surface of the lower one of the polysilicon layers or metal silicide layers; a metal layer respectively disposed as a top surface and a lower bottom surface of the semiconductor structure to form a source and a drain as electrodes for the semiconductor structure to be connected to an external device.
    Type: Application
    Filed: February 24, 2023
    Publication date: August 31, 2023
    Inventors: Chih-Fang HUANG, JIA-WEI HU, FU-JEN HSU
  • Publication number: 20230205574
    Abstract: A system and method for storing data associated with a system management interrupt (SMI) in a computer system. Notification of a system management interrupt is received on a central processing unit. The central processing unit enters a system management mode. A system management handler of a basic input output system (BIOS) is executed by a bootstrap processor of the central processing unit. The system management interrupt is initiated via the bootstrap processor. The system management interrupt data is stored in a register of the bootstrap processor. The SMI data is converted to an accessible format. The converted SMI data is stored in a memory.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 29, 2023
    Inventors: Chih-Hsiang HSU, Wei-Wei LI, Shang-Lin TSAI, Lueh-Chih FANG
  • Publication number: 20230154752
    Abstract: Methods are provided herein for forming spacers on a patterned substrate. A self-aligned multiple patterning (SAMP) process is utilized for patterning structures, spacers formed adjacent mandrels, on a substrate. In one embodiment, a novel approach of etching titanium oxide (TiO2) spacers is provided. Highly anisotropic etching of the spacer along with a selective top deposition is provided. In one embodiment, an inductively coupled plasma (ICP) etch tool is utilized. The etching process may be achieved as a one-step etching process. More particularly, a protective layer may be selectively formed on the top of the spacer to protect the mandrel as well as minimize the difference of the etching rates of the spacer top and the spacer bottom. In one embodiment, the techniques may be utilized to etch TiO2 spacers formed along amorphous silicon mandrels using an ICP etch tool utilizing a one-step etch process.
    Type: Application
    Filed: November 12, 2021
    Publication date: May 18, 2023
    Inventors: Ya-Ming Chen, Katie Lutker-Lee, Eric Chih-Fang Liu, Angelique Raley, Stephanie Oyola-Reynoso, Shihsheng Chang
  • Patent number: 11651965
    Abstract: Embodiments are described herein that apply capping layers to cores prior to spacer formation in self-aligned multiple patterning (SAMP) processes to achieve vertical spacer profiles. For one embodiment, a plasma process is used to deposit a capping layer on cores, and this capping layer causes resulting core profiles to have protective caps. These protective caps formed with the additional capping layer help to reduce or minimize material loss and corner loss of the core material during spacer deposition and spacer etch processes. This reduction in core material loss improves the resulting spacer profile so that a more vertical profile is achieved. For one embodiment, an angle of 80-90 degrees is achieved for vertical sidewalls of the spacers adjacent core sites with respect to the horizontal surface of the underlying layer, such as a hard mask layer formed on a substrate for a microelectronic workpiece.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: May 16, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Eric Chih-Fang Liu, Akiteru Ko
  • Patent number: 11645130
    Abstract: A resource manager (RM) instance is associated with each transaction processing system (TPS) member, of a TPS group. Each RM instance monitors performance of the associated TPS member. If a TPS member becomes unavailable for any reason (a failing TPS), the associated RM instance broadcasts status of the failing TPS to RMs associated “surviving” members of the group. RM instances associated with surviving members initiate a series of actions that reduce the resources used by the surviving TPS members. Consequently, the surviving TPS members are better able to process the additional workload imposed on them due to the unavailability of the failing TPS. Once the failing TPS is brought back online and made available again (or a replacement TPS is brought online), RM instances associated with the surviving members perform actions to undo the resource usage reduction tasks, and the TPS group returns to a nominal configuration.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: May 9, 2023
    Assignee: International Business Machines Corporation
    Inventors: Jack Chiu-Chiu Yuan, Jeffrey L. Maddix, Elvis B. Halcrombe, Chih-Fang Li
  • Publication number: 20230052659
    Abstract: A signal processing method includes the following operations: receiving an input signal and analyzing the input signal to generate a plurality of bit codes by a signal receiving circuit; temporarily storing a first part of the plurality of bit codes according to a time sequence by a shift register and starting a decoder when the shift register is full; and performing a boundary calibration according to the first part of the plurality of bit codes by the decoder when the first part of the plurality of bit codes meets a decoding table rule and a boundary detection rule.
    Type: Application
    Filed: December 29, 2021
    Publication date: February 16, 2023
    Inventors: Hong-Ru CHOU, Wen-Chih FANG, Yung-Le CHANG, Bo-Cheng LIN
  • Publication number: 20230037027
    Abstract: A multidrop network system includes N network devices. The N network devices include a master device and multiple slave devices, and each network device has an identification code as its own identification in the multidrop network system. The N network devices have N identification codes and obtain transmission opportunities in turn according to the N identification codes in each round of data transmission. Each network device performs a count operation to generate a current count value, and when the identification code of a network device is the same as the current count value, this network device obtains a transmission opportunity. After a device obtains the transmission opportunity, it determines whether a cut-in signal from another network device is observed in a front duration of a predetermined time slot, and then determines whether to abandon/defer the right to start transmitting in the remaining duration of the predetermined time slot.
    Type: Application
    Filed: May 31, 2022
    Publication date: February 2, 2023
    Inventors: YUNG-LE CHANG, WEN-CHIH FANG, DENG-SHIAN WANG, SHIEH-HSING KUO
  • Publication number: 20230023626
    Abstract: A fan blade device includes a plurality of main fan blades and extension fan blades. Each main fan blade includes a main fan blade body arranged obliquely, a plurality of first protrusions, and at least one engaging groove. Each extension fan blade includes an extension fan blade body arranged obliquely and having a top surface that is contiguously flush with a top surface of the main fan blade body of a respective main fan blade, a plurality of second protrusions respectively abutting against the first protrusions of the respective main fan blade, and at least one engaging piece engaging the at least one engaging groove of the respective main fan blade.
    Type: Application
    Filed: February 22, 2022
    Publication date: January 26, 2023
    Inventors: Chang-Sung WANG, Mei-Chih FANG
  • Publication number: 20230021997
    Abstract: A multidrop network system includes N network devices. The N network devices includes M transmission-permissible devices including a master device and at least one slave device, wherein M is not greater than N. Each transmission-permissible device has at least one identification code as its identification in the multidrop network system, and the M transmission-permissible devices have at least N identification codes. The M transmission-permissible devices obtain transmission opportunities in turn according to their respective identification codes in each round of data transmission. A Kth device among the M transmission-permissible devices has multiple identification codes, and thus obtains multiple transmission opportunities in one round of data transmission.
    Type: Application
    Filed: July 19, 2022
    Publication date: January 26, 2023
    Inventors: YUNG-LE CHANG, WEN-CHIH FANG, DENG-SHIAN WANG, SHIEH-HSING KUO
  • Patent number: 11557479
    Abstract: Methods process microelectronic workpieces with inverse extreme ultraviolet (EUV) patterning processes. In part, the inverse patterning techniques are applied to reduce or eliminate defects experienced with conventional EUV patterning processes. The inverse patterning techniques include additional process steps as compared to the conventional EUV patterning processes, such as an overcoat process, an etch back or planarization process, and a pattern removal process. In addition, further example embodiments combine inverse patterning techniques with line smoothing treatments to reduce pattern roughness and achieve a target level of line roughness. By using this additional technique, line pattern roughness can be significantly improved in addition to reducing or eliminating microbridge and/or other defects.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: January 17, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Eric Chih-Fang Liu, Akiteru Ko, Subhadeep Kal, Toshiharu Wada
  • Patent number: 11549519
    Abstract: A fan blade device includes a plurality of main fan blades and extension fan blades. Each main fan blade includes a main fan blade body arranged obliquely, a plurality of first protrusions, and at least one engaging groove. Each extension fan blade includes an extension fan blade body arranged obliquely and having a top surface that is contiguously flush with a top surface of the main fan blade body of a respective main fan blade, a plurality of second protrusions respectively abutting against the first protrusions of the respective main fan blade, and at least one engaging piece engaging the at least one engaging groove of the respective main fan blade.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: January 10, 2023
    Assignee: YEN SUN TECHNOLOGY CORP.
    Inventors: Chang-Sung Wang, Mei-Chih Fang