Abstract: A manufacturing method of a chip package structure includes: dicing a wafer to separate chips formed thereon; mounting the chips on a carrier, wherein an active surface and pads of each chip are buried in an adhesive layer disposed on the carrier, and a top surface of the adhesive layer between the chips is bulged away from the carrier; forming an encapsulant to encapsulate the chips and cover the adhesive layer, wherein the encapsulant has a concave surface covering the top surface of the adhesive layer and a back surface opposite to the concave surface; removing the carrier and the adhesive layer; forming a first dielectric layer to cover the concave surface and the active surface; forming a patterned circuit layer on the first dielectric layer, to electrically connect to the pads through openings in the first dielectric layer; and forming a second dielectric layer on the patterned circuit layer.

Abstract: A backhaul bandwidth management method for a wireless network is provided. Firstly, a backhaul connection mode is adjusted by a network device in a backhaul network according to a wireless capability. Then, a backhaul guaranteed bandwidth is guaranteed by the network device according to at least one of a dedicated service set identifier (SSID), a dedicated radio frequency (RF) band and a dedicated wireless mode. Then, a bandwidth allocation algorithm is executed by the network device to ensure that at least one backhaul transmission connection has the backhaul guaranteed bandwidth. Finally, a backhaul SSID is set to a first wireless network standard only mode by the network device to ensure that data transmission will not be interfered with by other network devices transmitting data according to a second wireless network standard in the backhaul network.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a top semiconductor die, a bottom semiconductor die, a first encapsulant, a second encapsulant, a third encapsulant, a first redistribution layer and a second redistribution layer. The top semiconductor die is stacked on the bottom semiconductor die. The bottom semiconductor die is laterally encapsulated by the third encapsulant, and the third encapsulant is laterally surrounded by the first encapsulant. The top semiconductor die is laterally encapsulated by the second encapsulant. The first redistribution layer is disposed between the top and bottom semiconductor dies. The bottom semiconductor die, the first encapsulant and the third encapsulant are located between the first and second redistribution layers.

Abstract: A vaporization pipe for a kerosene lamp has an oil tube, a thermally conductive tube, and a first passage. The oil tube is made of steel and has a vaporization jet on a top of the oil tube. The thermally conductive tube is mounted in the oil tube and forms a first channel. The first passage is disposed between the oil tube and the thermally conductive tube. The steel oil tube can prevent the vaporization pipe from being softened and bent during the preheating of vaporization pipe or burning of the kerosene, and thus a useful lifetime of the vaporization pipe is prolonged. The thermally conductive tube is made of high-thermal-conductivity material for keeping the vaporization pipe with adequate thermal conductivity and improving a burning rate of kerosene. The first passage allows the kerosene to flow upward, preventing the kerosene from being vaporized incompletely because the kerosene is over pressurized.

Abstract: Methods and systems for line cut by multi-color patterning techniques are presented. In an embodiment, a method may include providing a substrate. The method may also include forming a first feature on the substrate, the first feature having a cap formed of a first material. Additionally, the method may include forming a second feature on the substrate, the second feature having a cap formed of a second material. In still a further embodiment, the method may include selectively removing the second feature using an etch process that etches the first material at a first etch rate and etches the second material at a second etch rate, wherein the second etch rate is higher than the first etch rate.

Abstract: A semiconductor device package includes a substrate, a connection structure, a first package body and a first electronic component. The substrate has a first surface and a second surface opposite to the first surface. The connection structure is disposed on the firs surface of the substrate. The first package body is disposed on the first surface of the substrate. The first package body covers the connection structure and exposes a portion of the connection structure. The first electronic component is disposed on the first package body and in contact with the portion of the connection structure exposed from the first package body.

Abstract: Embodiments are disclosed for processing microelectronic workpieces to apply stress engineering to self-aligned multi-patterning (SAMP) processes. The disclosed processing methods utilize stress in a substrate in a SAMP process to improve resulting pattern parameters. Initially, a high stress film is deposited on the frontside and the backside of the substrate, and the high stress film provides biaxial stress to the substrate due to the deposition process for the high stress film. Next, a SAMP process is performed to form spacers in a spacer pattern. This spacer pattern is then transferred to underlying layers to form a patterned structure. The high stress film provides axial stress in at least one direction along a portion of the patterned structure during the pattern transfer thereby improving resulting pattern formation.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a bumpless die including a plurality of conductive pads, a conductive connector disposed aside the bumpless die and electrically coupled to the bumpless die, an insulating encapsulation encapsulating the bumpless die and the conductive connector, a circuit layer electrically connected to the bumpless die and the conductive connector, and a front side redistribution layer disposed on the circuit layer and including a finer line and spacing routing than the circuit layer. The circuit layer includes a conductive pattern disposed on the insulating encapsulation and extending along a thickness direction of the bumpless die to be connected to the conductive pads of the bumpless die, and a dielectric pattern disposed on the insulating encapsulation and laterally covering the conductive pattern.

Abstract: A package structure includes a redistribution structure, a bridge die, a plurality of conductive pillars, at least two dies, and an insulating encapsulant. The bridge die provides an electrical connection between the at least two dies. The conductive pillars provide an electrical connection between the at least two dies and the redistribution structure. The insulating encapsulant is disposed on the redistribution structure, encapsulates the bridge die and the conductive pillars, and covers each of the at least two dies. The bridge die of the package structure may be used to route signals between the at least two dies, allowing for a higher density of interconnecting routes between the at least two dies.

Abstract: Disclosed herein is an improved pharmaceutical management system and methods implemented by the system for sorting and identifying a medicine via its label and/or package. The method comprises steps of: (1) receiving a plurality of raw images of a package of a medication; (b) juxtaposing two of the plurality of raw images to produce a combined image, in which the two raw images are different from each other; (c) processing the combined image to produce a reference image; and (d) establishing the medication library with the aid of the reference image. The system comprises an image capturing device, an image processor, and a machine learning processor. The image processor is programmed with instructions to execute the method for producing a combined image.

Abstract: A method is provided for void-free Ru metal filling of features in a substrate. The method includes providing a substrate containing features, depositing a Ru metal layer in the features, removing the Ru metal layer from a field area around an opening of the features, and depositing additional Ru metal in the features, where the additional Ru metal is deposited in the features at a higher rate than on the field area. According to one embodiment, the additional Ru metal is deposited until the features are fully filled with Ru metal.

Abstract: A hiking shoe includes a vamp connected to an outsole. The outsole includes a rear section and a front section. The outsole has multiple anti-slip blocks formed thereto. Multiple spikes are respectively and integrally formed to a portion of the anti-slip blocks that are located at the rear section and the front section of the outsole. Each spike has an end face that is formed on the first end thereof, and the end face is in flush with the distal end of the anti-slip block corresponding thereto. The second end of each spike is located within the anti-slip block corresponding thereto and within the outsole. The end face of each spike has multiple grooves defined therein so as to provide friction. Each spike is made by SKD-11 (Steel Kogu Dies-11).

Abstract: A manufacturing method of a stacked chip package structure includes the following steps. A first chip is disposed on a carrier, wherein the first chip has a first active surface and a plurality of first pads disposed on the first active surface. A second chip is disposed on the first chip without covering the first pads and has a second active surface and a plurality of second pads disposed on the second active surface. A plurality of first stud bumps are formed on the first pads. A plurality of pillar bumps are formed on the second pads. The first chip and the second chip are encapsulated by an encapsulant, wherein the encapsulant exposes a top surface of each second stud bump. A plurality of first vias are formed by a laser process, wherein the first vias penetrate the encapsulant and expose the first stud bumps. A conductive layer is formed in the first vias to form a plurality of first conductive vias. The carrier is removed.

Abstract: The invention provides a system and method for detecting clock frequency offset of fan chip. The system comprises a fan chip and a control unit. A target pulse width is defined in the fan chip and the control unit. When the control unit executes a detection process of clock frequency offset for the fan chip, it will generate a specific pattern pulse signal and send the specific pattern pulse signal to the fan chip. The fan chip enters a detection mode of clock frequency offset according to the specific pattern pulse signal, generates a response signal including an actual target pulse width based on referring to the defined target pulse width, and send the response signal to the control unit. The control unit compares a difference between the actual target pulse width and the defined target pulse width to detect a clock frequency offset value of the fan chip.

Abstract: A repeater configured to be connected to a network is provided. The repeater includes an uplink wireless transmission interface, a downlink wireless transmission interface, and a processing unit. The uplink wireless transmission interface is configured to establish an external wireless connection with the network. The downlink wireless transmission interface is configured to perform data transmission with the uplink wireless transmission interface and has an external wireless transmission function. The processing unit is configured to turn off the external wireless transmission function of the downlink wireless transmission interface when the connection between the uplink wireless transmission interface and the network is disconnected.

Abstract: A network device including an Ethernet transmission interface and a processing unit is provided. The Ethernet transmission interface is provided with at least one Ethernet transmission port. The processing unit is coupled to the Ethernet transmission interface and is configured to: in order to detect whether a packet looping exists, send out a dynamic host configuration protocol (DHCP) discover message through a linked Ethernet transmission port in response to linking one of the at least one Ethernet transmission port to a network and determine whether a DHCP offer message is received; determine whether to prohibit data transmission of the linked Ethernet transmission port according to whether the DHCP discover message returned through the packet looping is detected; classify the linked Ethernet transmission port as an uplink transmission port or a downlink transmission port according to whether the DHCP offer message is received.

Abstract: The invention provides a fan control system, which comprises a fan, a control unit, and a fan chip. The fan chip comprises a command table. A first specific pulse pattern represented as a first form of code, and a second specific pulse pattern represented as a second form of code are defined in the fan chip. The command table records at least one control command. Each control command is corresponding to a code string, respectively. When the fan chip receives a series of pulse signals from the control unit, it will determine that the code string is represented by the pulse signals, and inquire the corresponding control command from the command table according to the determinated code string so as to set up at least one operation parameter of the fan chip or control the fan to perform a corresponding operation according to the inquired control command.

Abstract: A package structure including a die, a plurality of first conductive connectors, a second conductive connector electrically insulated from the die, a redistribution layer and a conductive shield is provided. The die includes an active surface, a back surface opposite the active surface, and a sidewall coupling the active surface to the back surface. The first conductive connectors are disposed on the active surface of the die and electrically connected to the die. The second conductive connector is disposed on the die and aside the first conductive connectors. The redistribution layer is disposed on the die and electrically connected to the first conductive connectors and the second conductive connector. The conductive shield coupled to the redistribution layer surrounds the second conductive connector and at least a portion of the sidewall. The die is electrically insulated to the conductive shield. A chip package structure is also provided.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a conductive casing, a semiconductor die, a conductive connector, an insulating encapsulant, a redistribution structure, and a first conductive terminal. The conductive casing has a cavity. The semiconductor die is disposed in the cavity of the conductive casing. The conductive connector is disposed on a periphery of the conductive casing. The insulating encapsulant encapsulates the conductive connector, the semiconductor die and the cavity. The redistribution structure is formed on the insulating encapsulant and is electrically connected to the conductive connector and the semiconductor die. The first conductive terminal is disposed in openings of the redistribution structure and is physically in contact with a portion of the conductive casing.

Abstract: A hiking shoe includes a vamp connected to an outsole. Multiple anti-blocks are formed on the underside and multiple spikes are respectively embedded in the anti-slip blocks that are located between the rear section and the front section of the underside of the outsole. Each spike has an end face that is formed on the first end thereof, and the end face is in flush with the distal end of the anti-slip block corresponding thereto. The second end of each spike is located within the anti-slip block corresponding thereto. The end face of each spike has multiple grooves defined therein so as to provide better anti-slip feature when walking on a wet path with pebbles.