Abstract: Embodiments are described herein to reduce formation of undesired particles during plasma processing for microelectronic workpieces by depositing a layer (e.g., think film) on the surface of a chuck, such as an electrostatic chuck (ESC), prior to plasma processing such as a plasma etch process (e.g., a reactive ion etch (RIE) process) and/or a plasma deposition process. This layer works as a lubricant or protective coating to reduce or minimize physical contact between the microelectronic workpiece (e.g., semiconductor wafer) and the chuck. This reduction in physical contact reduces scratching of the backside of the microelectronic workpiece and reduces related formation of undesired particles that can be transported to the front side of the microelectronic workpiece and cause defects and reduce yields. As such, the disclosed embodiments improve particle (PA) performance parameters for plasma etch and/or deposition processes.

Abstract: A shoe includes an outsole having a room defined in the top thereof. A vamp is connected to the peripheral wall of the room. An air pad and an insole are located in the room. The air pad includes a front pad and a rear pad. A tube is connected between the front and rear pads. The front pad includes an inflatable support portion and a resilient support section which is located at the front portion of the front pad. The resilient support section has multiple buffering portions. A plate is located on the front pad and between the inflatable support portion and the insole. The plate restricts the deformation area on the inflatable support portion to deform the insole.

Abstract: A footwear assembly includes a shoe having a vamp and an outsole. The shoe includes a first room defined between the vamp and the outsole, and a first opening is formed in the top of the shoe and communicates with the first room. A first connection member is located on outside of the first opening. A water-proof sock is inserted in the first room via the first opening, and has a neck portion formed along the second opening of the water-proof sock. The neck portion is able to be foldable relative to the water-proof sock and has a second connection member which is connected to the first connection member when the neck portion is foldable relative to the water-proof sock.

Abstract: This disclosure relates to a high volume manufacturing system for processing and measuring workpieces in a semiconductor processing sequence without leaving the system's controlled environment (e.g., sub-atmospheric pressure). The systems process chambers are connected to each other via transfer chambers used to move the workpieces, in the controlled environment, between the process chambers. Further, the pass-through chambers may be disposed between the transfer chambers or between the transfer chamber and the process chamber. The pass-through chambers may include a measurement region to measure workpiece attributes when the workpiece is moved through or placed in the pass-through chamber. The transfer chambers may also have separate measurement regions within their internal space to measure other attributes of the workpiece.

Abstract: A semiconductor package includes a semiconductor die, a first redistribution structure, a conductive structure, and an insulating encapsulant. The first redistribution structure includes a dielectric protrusion. The first redistribution structure includes a die attach region and a peripheral region surrounding the die attach region. The semiconductor die is disposed on the first redistribution structure within the die attach region. The dielectric protrusion is disposed in the peripheral region and extends in a thickness direction of the semiconductor die. The conductive structure is disposed on the first redistribution structure within the in the peripheral region and encapsulates the semiconductor dielectric protrusion. The conductive structure is electrically coupled to the first redistribution structure and the semiconductor die. The insulator is disposed on the first redistribution structure and encapsulates the semiconductor die and the conductive structure.

Abstract: A touch and/or display panel with minimal border area includes a first substrate with first and second opposite surfaces. The panel further comprises a film on the first surface and bent to the second surface, the film is flexible and wires are patterned into the film. The film comprises first and second ends, the first end is located on the first surface, and the second end is located on the second surface and a chip is formed on the second end. A method for making the panel is also disclosed.

Abstract: A structure of a trench metal-oxide-semiconductor field-effect transistor includes an N-current spread layer (N-CSL) disposed on the N-drift region a split gate structure formed in the gate trench and covered by the insulating layer; and a semiconductor protection layer disposed below the bottom of the trench and adjacent to the N-drift region, wherein the insulating layer is disposed above the semiconductor protection layer to protect the insulating layer from being broken through by an electric field when the structure turns off a bias; wherein the gate is separated from the split gate by the insulating layer to form a predetermined gap; and a depth position of a bottom of the trench gate is deeper than an interface between the P-well and the N-current spread layer.

Abstract: A structure of a trench metal-oxide-semiconductor field-effect transistor includes an N-current spread layer (N-CSL) disposed on the N-drift region a split gate structure formed in the gate trench and covered by the insulating layer; and a semiconductor protection layer disposed below the bottom of the trench and adjacent to the N-drift region, wherein the insulating layer is disposed above the semiconductor protection layer to protect the insulating layer from being broken through by an electric field when the structure turns off a bias; wherein the gate is separated from the split gate by the insulating layer to form a predetermined gap; and a depth position of a bottom of the trench gate is deeper than an interface between the P-well and the N-current spread layer.

Abstract: Methods and systems for in-situ spacer reshaping for self-aligned multi-patterning are described. In an embodiment, a method of forming a spacer pattern on a substrate may include providing a substrate with a spacer. The method may also include performing a passivation treatment to form a passivation layer on the spacer. Additionally, the method may include performing spacer reshaping treatment to reshape the spacer. The method may also include controlling the passivation treatment and spacer reshaping treatment in order to achieve spacer formation objectives.

Abstract: The invention provides a detection system and method of signal transmission delay for fan chip. The detection system comprises a circuit board, a fan chip and a control unit. The control unit generates a first pulse signal having a specific pulse pattern, and send the first pulse signal to the fan chip. When the fan chip is operating in a detection mode of signal transmission delay according to the first pulse signal, the fan chip copies the specific pulse pattern of the first pulse signal to generate a second pulse signal having the specific pulse pattern, and send the second pulse signal to the control unit. The control unit calculates a time difference between a time that sends the first pulse signal and a time that receives the second pulse signal, so as to obtain a delay time of signal transmission between the control unit and the fan chip.

Abstract: A semiconductor package including a stacked-die structure, a second encapsulant laterally encapsulating the stacked-die structure and a redistribution layer disposed on the second encapsulant and the staked-die structure is provided. The stacked-die structure includes a first semiconductor die including a first active surface, a circuit layer disposed on the first active surface, a second semiconductor die including a second active surface facing towards the first active surface, a plurality of conductive features distributed at the circuit layer and electrically connected to the first and second semiconductor die and a first encapsulant encapsulating the second semiconductor die and the conductive features. A portion of the conductive features surrounds the second semiconductor die. The redistribution layer is electrically connected to the staked-die structure. A manufacturing method of a semiconductor package is also provided.

Abstract: A power semiconductor device includes a substrate, a main body and an electrode unit. The main body includes an active portion, an edge termination portion surrounding the active portion, and an insulating layer disposed on the edge termination portion. The edge termination portion includes a first-type semiconductor region, and a plurality of spaced-apart second-type semiconductor segments distributed in the first-type semiconductor region and arranged at intervals along a Y-direction directing from the insulating layer toward the substrate, and an X-direction directing from the active portion toward the edge termination portion. The electrode unit includes a first electrode and a second electrode.

Abstract: Methods and systems for line cut by multi-color patterning techniques are presented. In an embodiment, a method may include providing a substrate. The method may also include forming a first feature on the substrate, the first feature having a cap formed of a first material. Additionally, the method may include forming a second feature on the substrate, the second feature having a cap formed of a second material. In still a further embodiment, the method may include selectively removing the second feature using an etch process that etches the first material at a first etch rate and etches the second material at a second etch rate, wherein the second etch rate is higher than the first etch rate.

Abstract: The invention provides a fan control system, which comprises a fan, a control unit, and a fan chip. The fan chip comprises a command table. A first specific pulse pattern represented as a first form of code, and a second specific pulse pattern represented as a second form of code are defined in the fan chip. The command table records at least one control command. Each control command is corresponding to a code string, respectively. When the fan chip receives a series of pulse signals from the control unit, it will determine that the code string is represented by the pulse signals, and inquire the corresponding control command from the command table according to the determinated code string so as to set up at least one operation parameter of the fan chip or control the fan to perform a corresponding operation according to the inquired control command.

Abstract: A stacked package has plurality of chip packages stacked on a base. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on a lateral side of the chip package. The lateral trace is formed through the encapsulant and electrically connects to the cut edges of the chip packages. The base has an interconnect structure to form the electrical connection between the lateral trace and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.

Abstract: A semiconductor package including a stacked-die structure, a second encapsulant laterally encapsulating the stacked-die structure and a redistribution layer disposed on the second encapsulant and the staked-die structure is provided. The stacked-die structure includes a first semiconductor die including a first active surface, a circuit layer disposed on the first active surface, a second semiconductor die including a second active surface facing towards the first active surface, a plurality of conductive features distributed at the circuit layer and electrically connected to the first and second semiconductor die and a first encapsulant encapsulating the second semiconductor die and the conductive features. A portion of the conductive features surrounds the second semiconductor die. The redistribution layer is electrically connected to the staked-die structure. A manufacturing method of a semiconductor package is also provided.

Abstract: A network device, which can be disposed in a mesh network, and include a WPS button and a processing circuit. The WPS button may trigger a WPS connection process. The processing circuit may be connected to the WPS button. The processing circuit can determine whether the uplink connection of the network device exists; if the uplink connection of the network device does not exist, the processing circuit can implement an uplink connection process; if the uplink connection of the network device exists, the processing circuit can implement a downlink connection process.

Abstract: A network path selection method and a network node device using the same are provided. The network path selection method is used for selecting a path connected to a mesh network from the network node device. The network path selection method includes the following steps. The network node device is connected to a gateway device via at least one first relay node device. A first communication performance of the first relay node device is measured. The network node device is connected to the gateway device via at least one second relay node device. A second communication performance of the second relay node device is measured. The network node device is selectively connected to the gateway device via the first relay node device or the second relay node device according to the first communication performance and the second communication performance.

Abstract: A shoe includes an outsole having a room defined in the top thereof. A vamp is connected to the peripheral wall of the room. An air pad and an insole are located in the room. The air pad includes a front pad and a rear pad. A tube is connected between the front and rear pads. The front pad includes an inflatable support portion and a resilient support section which is located at the front portion of the front pad. The resilient support section has multiple buffering portions. A plate is located on the front pad and between the inflatable support portion and the insole. The plate restricts the deformation area on the inflatable support portion to deform the insole.

Abstract: A network device including an Ethernet transmission interface and a processing unit is provided. The Ethernet transmission interface is provided with at least one Ethernet transmission port. The processing unit is coupled to the Ethernet transmission interface and is configured to: in order to detect whether a packet looping exists, send out a dynamic host configuration protocol (DHCP) discover message through a linked Ethernet transmission port in response to linking one of the at least one Ethernet transmission port to a network and determine whether a DHCP offer message is received; determine whether to prohibit data transmission of the linked Ethernet transmission port according to whether the DHCP discover message returned through the packet looping is detected; classify the linked Ethernet transmission port as an uplink transmission port or a downlink transmission port according to whether the DHCP offer message is received.