Abstract: A memory cell includes patterning a first trench extending through a first conductive line, depositing a memory film along sidewalls and a bottom surface of the first trench, depositing a channel layer over the memory film, the channel layer extending along the sidewalls and the bottom surface of the first trench, depositing a first dielectric layer over and contacting the channel layer to fill the first trench, patterning a first opening, wherein patterning the first opening comprises etching the first dielectric layer, depositing a gate dielectric layer in the first opening, and depositing a gate electrode over the gate dielectric layer and in the first opening, the gate electrode being surrounded by the gate dielectric layer.

Abstract: The invention provides an anti-allergic peptide and a use thereof for immune regulation and anti-allergy, the anti-allergic peptide is capable of inhibiting secretion of cytokines related to allergic reactions and regulating allergic reactions, and the anti-allergic peptide comprises an amino acid sequence shown in SEQ ID No: 1, SEQ ID No: 2, SEQ ID No: 3, SEQ ID No: 4 or SEQ ID No: 5, or a homologous amino acid sequence derived from substitution, deletion, and addition of one amino acid or more than one amino acid of any of the above sequences.

Abstract: A semiconductor device includes an insulating layer, wherein the insulating layer has a via opening and a conductive line opening. The semiconductor device further includes a via in the via opening. The semiconductor device further includes a conductive line in the conductive line opening. The conductive line includes a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and a conductive fill, wherein the first liner layer surrounds the conductive fill.

Abstract: Three-dimensional integrated circuit (3DIC) structures and methods of forming the same are provided. A 3DIC structure includes a semiconductor package, a first package substrate, a molded underfill layer and a thermal interface material. The semiconductor package is disposed over and electrically connected to the first package substrate through a plurality of first bumps. The semiconductor package includes at least one semiconductor die and an encapsulation layer aside the semiconductor die. The molded underfill layer surrounds the plurality of first bumps and a sidewall of the semiconductor package, and has a substantially planar top surface. The CTE of the molded underfill layer is different from the CTE of the encapsulation layer of the semiconductor package. The thermal interface material is disposed over the semiconductor package.

Abstract: A memory cell includes a transistor including a memory film extending along a word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; a source line extending along the memory film, wherein the memory film is between the source line and the word line; a first contact layer on the source line, wherein the first contact layer contacts the channel layer and the memory film; a bit line extending along the memory film, wherein the memory film is between the bit line and the word line; a second contact layer on the bit line, wherein the second contact layer contacts the channel layer and the memory film; and an isolation region between the source line and the bit line.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy, gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

Abstract: A semiconductor package includes a die attach pad; a plurality of lead terminals disposed around the die attach pad; a semiconductor die mounted on the die attach pad; a molding compound encapsulating the plurality of lead terminals, the semiconductor die, and the die attach pad; and a step cut sawn into the molding compound along a perimeter of a bottom surface of the semiconductor package. The step cut penetrates through an entire thickness of each of the plurality of lead terminals, whereby each of the plurality of lead terminals has at least an exposed outer end at the step cut.

Abstract: An antenna device including an antenna structure, a base, an elastic bracket, a restriction unit, and a fastener is provided. The base is connected to the antenna structure. The base includes a plurality of grooves. The elastic bracket includes a plurality of elastic legs. Each of the elastic legs includes a free end. The free end is guided by the corresponding groove. The elastic legs abut the restriction unit. The fastener affix the restriction unit to the base. At least a portion of the elastic bracket is disposed between the restriction unit and the base.

Abstract: A 3-dimensional (3D) integrated circuit (IC) is provided. The 3D IC includes a plurality of chips, at least one through silicon via (TSV) structure, and a temperature sensor. The chips are stacked in the 3D IC. The TSV structure penetrates the chips. The temperature sensor is disposed in a first chip of the chips. The temperature sensor is disposed close to the TSV structure, and is configure to sense a temperature sensing result corresponding to a temperature of the TSV structure.

Abstract: A media streaming device includes a power manager, a stream processor, and a voltage detector. The power manager receives a power signal from the media playback device to supply power to the stream processor. The stream processor provides media stream to the media playback device for playback. The voltage detector is electrically coupled to the stream processor and captures at least a part of the power supply current to the stream processor. The stream processor is configured to determine whether the power supply voltage remains stable. When the supply voltage remains stable, the stream processor operates in a first mode to provide media stream. When the power supply voltage is unstable, the stream processor operates in a second mode to provide media stream, and the power consumption of the stream processor in the second mode is lower than the power consumption in the first mode.

Abstract: An RFID tag for high frequency (HF) or low frequency (LF) with metal protection is provided, including: an electronic tag, a metal protective piece and an insulator. The electronic tag includes a loop antenna and a control chip set electrically connected thereto; the metal protective piece is arranged around the loop antenna shape and is a non-closed ring-shaped metal piece; the insulator covers the electronic tag and is fixed on the metal protective piece, and the insulator prevents the loop antenna and the metal protective piece from contacting with each other; the control chipset is pre-adjusted so that the loop antenna and the metal protective piece are at the same operating frequency. The non-closed ring-shaped metal protective piece protects the electronic tag so that it is not easily damaged, and can be used to sense HF or LF signals.

Abstract: A multi-channel memory device includes N first memory blocks, a first redundancy memory block, and N first interface circuits. Each of the first interface circuits is coupled to two of the first memory blocks and the first redundancy memory block. The first interface circuits respectively select N first selected memory blocks in the first memory block and the first redundancy memory block according to a plurality of first selection signals, where N is a positive integer greater than 1.

Abstract: The control circuit for controlling a display panel is provided. The control circuit includes a first driving circuit and a second driving circuit for driving the display panel. The first driving circuit includes first output terminals and first input terminals. The first driving circuit outputs a plurality of test signals to the first output terminals sequentially during different periods in a diagnosis stage. The second driving circuit includes second input terminals and second output terminals. The second driving circuit receives the test signals through the second input terminals in the diagnosis stage, and outputs a plurality of response signals to the second output terminals sequentially during different periods in response to the test signals. The first driving circuit receives the response signals through the first input terminals, and judges a connecting status of the first driving circuit and the second driving circuit according to the response signals.

Abstract: System on chips, memory circuits, and method for data access, the memory circuits including a memory cell array and an input/output (I/O) connection interface coupled to the memory cell array, wherein the I/O connection interface is configured for coupling to an external signal line to directly receive a transistor-level operation signal from an external memory controller for accessing data in the memory cell array.

Abstract: A random-number-generating circuit is provided, which includes a noise-voltage generator, a voltage-controlled oscillator, a ring oscillator, and a D flip-flop (DFF). The noise-voltage generator converts an external voltage into a noise voltage. The voltage-controlled oscillator receives the noise voltage, and generates a first clock signal according to the noise voltage. The ring oscillator generates a sampling clock signal. The DFF receives the first clock signal, and samples the first clock signal using the sampling clock signal to obtain an output digital signal, wherein the output digital signal represents a random number.

Abstract: A low-dropout regulator including a first comparator, an edge trigger, a second comparator, a third comparator, and an output stage circuit is provided. The first comparator generates a first comparison signal according to a first reference signal and an output signal. The edge trigger outputs a trigger signal according to the first comparison signal, a second comparison signal, and a third comparison signal. The second comparator generates the second comparison signal according to the output signal and a second reference signal. The third comparator generates the third comparison signal according to the output signal and a third reference signal. The output stage circuit outputs the output signal according to the first comparison signal, the second comparison signal, and the third comparison signal. The output stage circuit includes a plurality of hysteresis controllers and a plurality of power transistors. Each hysteresis controller controls a conduction state of a corresponding power transistor.

Abstract: An electrostatic discharge (ESD) protection device including the following components is provided. A first transistor includes a first gate, a first N-type source region, and an N-type drain region. A second transistor includes a second gate, a second N-type source region, and the N-type drain region. The N-type drain region is located between the first gate and the second gate. An N-type drift region is located in a P-type substrate between the first gate and the second gate and is located directly below a portion of the first gate and directly below a portion of the second gate. The N-type drain region is located in the N-type drift region. A P-type barrier region is located in the P-type substrate below the N-type drift region. The P-type barrier region has an overlapping portion overlapping the N-type drift region. There is at least one first opening in the overlapping portion.

Abstract: Disclosed is a power control system with zero voltage switching including a power controller, a rectification unit, a power unit, a transformer unit, a primary side switch unit, a current sensing unit, an auxiliary switch unit, an output unit, and a current sensing unit for implementing a function of flyback power conversion. The power controller has a power pin, a ground pin, a primary side driving pin, a voltage sensing pin, an auxiliary driving pin, and an auxiliary winding sensing pin, In particular, the auxiliary switch unit is controlled to influence an primary side winding through an auxiliary winding so as to reduce the drain voltage of the primary side switch unit. Further, the primary side switch unit is turned on when the drain voltage is decreased to the lowest value, thereby greatly reducing switching loss and increasing efficiency of power conversion.

Abstract: A media streaming device includes a power manager, a stream processor, and a voltage detector. The power manager receives a power signal from the media playback device to supply power to the stream processor. The stream processor provides media stream to the media playback device for playback. The voltage detector is electrically coupled to the stream processor and captures at least a part of the power supply current to the stream processor. The stream processor is configured to determine whether the power supply voltage remains stable. When the supply voltage remains stable, the stream processor operates in a first mode to provide media stream. When the power supply voltage is unstable, the stream processor operates in a second mode to provide media stream, and the power consumption of the stream processor in the second mode is lower than the power consumption in the first mode.