Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a multi-layer stack disposed on a substrate and having a plurality of conductive layers interleaved between a plurality of dielectric layers. A channel layer is arranged along a side of the multi-layer stack. A ferroelectric material is arranged between the channel layer and the side of the multi-layer stack. A plurality of oxygen scavenging layers are respectively arranged between the ferroelectric material and sidewalls of the plurality of conductive layers. The plurality of oxygen scavenger layers are entirely confined below the plurality of dielectric layers.

Abstract: A method includes forming a first conductive feature, depositing a graphite layer over the first conductive feature, patterning the graphite layer to form a graphite conductive feature, depositing a dielectric spacer layer on the graphite layer, depositing a first dielectric layer over the dielectric spacer layer, planarizing the first dielectric layer, forming a second dielectric layer over the first dielectric layer, and forming a second conductive feature in the second dielectric layer. The second conductive feature is over and electrically connected to the graphite conductive feature.

Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Abstract: A smart cloth includes a cloth body, a control body, actuation air-permeable components, temperature sensing components, and a health-monitoring device. The health-monitoring device includes a bio-sensing module, a blood glucose sensor, a blood pressure measurement module, and a gas bag. The temperature information of the wearer is detected by the temperature sensing components and outputted to the microprocessor of the control body, so that the microprocessor controls the actuation air-permeable components to perform the gas-guiding operation to adjust an apparent temperature of the wearer for providing wearing comfortableness. The bio-sensing module, the blood glucose sensing module, and the blood pressure measurement module detect and provide the detection data information for the wearer anytime and in real-time to provide health-related information to the wearer.

Abstract: A power supply has a housing, a circuit board, a wire, and a wire securing assembly. The wire securing assembly has a base plate and a securing structure. The securing structure has a first plate and a second plate. A side edge of the first plate is connected to the base plate. The second plate is spaced apart from the first plate. The wire is mounted through and between the first plate and the second plate. The wire securing assembly is modified from the current insulating part, in which the original side plate extends and forms an additional part, or a bent structure is added on the original side plate, and thus the additional structures become the securing structure. Thus, the wire is prevented from moving under vibration or external force and contacting the blades of the fan, or keeps in a position in compliance with safety requirements.

Abstract: A media streaming device includes a power manager, a stream processor, and a voltage detector. The power manager receives a power signal from the media playback device to supply power to the stream processor. The stream processor provides media stream to the media playback device for playback. The voltage detector is electrically coupled to the stream processor and captures at least a part of the power supply current to the stream processor. The stream processor is configured to determine whether the power supply voltage remains stable. When the supply voltage remains stable, the stream processor operates in a first mode to provide media stream. When the power supply voltage is unstable, the stream processor operates in a second mode to provide media stream, and the power consumption of the stream processor in the second mode is lower than the power consumption in the first mode.

Abstract: A fluid pump module includes a heat dissipation board assembly, a fixing frame body, fluid pumps, a control board and a conveying pipe is provided. The fixing frame body is fixed at one side of the heat dissipation board assembly, so as to form two accommodating spaces between the heat dissipation board assembly and the fixing frame body. Two fluid pumps are respectively disposed in the two accommodating spaces. The control board is disposed at another side of the heat dissipation board assembly. The conveying pipe connects the two fluid pumps in series so as to form a series connection therebetween. The control board controls operations of the fluid pumps, and the heat dissipation board assembly dissipates heats produced by a module formed by the two fluid pumps.

Abstract: An RFID tag for high frequency (HF) or low frequency (LF) with metal protection is provided, including: an electronic tag, a metal protective piece and an insulator. The electronic tag includes a loop antenna and a control chip set electrically connected thereto; the metal protective piece is arranged around the loop antenna shape and is a non-closed ring-shaped metal piece; the insulator covers the electronic tag and is fixed on the metal protective piece, and the insulator prevents the loop antenna and the metal protective piece from contacting with each other; the control chipset is pre-adjusted so that the loop antenna and the metal protective piece are at the same operating frequency. The non-closed ring-shaped metal protective piece protects the electronic tag so that it is not easily damaged, and can be used to sense HF or LF signals.

Abstract: A multi-channel memory device includes N first memory blocks, a first redundancy memory block, and N first interface circuits. Each of the first interface circuits is coupled to two of the first memory blocks and the first redundancy memory block. The first interface circuits respectively select N first selected memory blocks in the first memory block and the first redundancy memory block according to a plurality of first selection signals, where N is a positive integer greater than 1.

Abstract: The present disclosure provides a semiconductor processing apparatus according to one embodiment. The semiconductor processing apparatus includes a chamber; a base station located in the chamber for supporting a semiconductor substrate; a preheating assembly surrounding the base station; a first heating element fixed relative to the base station and configured to direct heat to the semiconductor substrate; and a second heating element moveable relative to the base station and operable to direct heat to a portion of the semiconductor substrate.

Abstract: A shapable display device includes a first deformable substrate, a first stretchable electrode layer, a stretchable display medium layer, and a second stretchable electrode layer. The first stretchable electrode layer is disposed on the first deformable substrate. The stretchable display medium layer is disposed on the first stretchable electrode layer. The second stretchable electrode layer is disposed on the stretchable display medium layer. The stretchable display medium layer is between the first stretchable electrode layer and the second stretchable electrode layer.

Abstract: An electrophoretic display device including a first stretchable material layer, a first stretchable electrode layer, a stretchable electrophoretic display medium layer, multiple second stretchable electrode layers, an insulation layer, and a third stretchable electrode layer. The first stretchable electrode layer is disposed on the first stretchable material layer. The stretchable electrophoretic display medium layer is disposed on the first stretchable electrode layer. The second stretchable electrode layers are separately disposed on the stretchable electrophoretic display medium layer, so that the stretchable electrophoretic display medium layer forms multiple display regions. The insulation layer is disposed on the second stretchable electrode layers, and has multiple through holes in which multiple conductive materials are respectively filled.

Abstract: A foldable display device includes a reflective display panel, a light guiding layer and at least one light source. The light guiding layer is located on the reflective display panel and includes a non-foldable area, a foldable area and a transition area. The light guiding layer satisfies the following formulas: D2<D1, W2?Rx ? and J1?(L?W2)/2?W1, in which D1 is a thickness of the non-foldable area, D2 is a thickness of the foldable area, W1 is a width of the non-foldable area, W2 is a width of the foldable area, R is a folding radius of the reflective display panel, J1 is a width of the transition area, L is a length of the light guiding layer. The light source is located on the reflective display panel and faces the sidewall of the light guiding layer.

Abstract: A molded semiconductor device includes a semiconductor device and a molding material encapsulating the semiconductor device, wherein an upper surface of the molding material is substantially coplanar with an upper surface of the semiconductor device and comprises a groove at least partially surrounding the upper surface of the semiconductor device.

Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.