Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.

Abstract: A random-number-generating circuit is provided, which includes a noise-voltage generator, a voltage-controlled oscillator, a ring oscillator, and a D flip-flop (DFF). The noise-voltage generator converts an external voltage into a noise voltage. The voltage-controlled oscillator receives the noise voltage, and generates a first clock signal according to the noise voltage. The ring oscillator generates a sampling clock signal. The DFF receives the first clock signal, and samples the first clock signal using the sampling clock signal to obtain an output digital signal, wherein the output digital signal represents a random number.

Abstract: A low-dropout regulator including a first comparator, an edge trigger, a second comparator, a third comparator, and an output stage circuit is provided. The first comparator generates a first comparison signal according to a first reference signal and an output signal. The edge trigger outputs a trigger signal according to the first comparison signal, a second comparison signal, and a third comparison signal. The second comparator generates the second comparison signal according to the output signal and a second reference signal. The third comparator generates the third comparison signal according to the output signal and a third reference signal. The output stage circuit outputs the output signal according to the first comparison signal, the second comparison signal, and the third comparison signal. The output stage circuit includes a plurality of hysteresis controllers and a plurality of power transistors. Each hysteresis controller controls a conduction state of a corresponding power transistor.

Abstract: An electrostatic discharge (ESD) protection device including the following components is provided. A first transistor includes a first gate, a first N-type source region, and an N-type drain region. A second transistor includes a second gate, a second N-type source region, and the N-type drain region. The N-type drain region is located between the first gate and the second gate. An N-type drift region is located in a P-type substrate between the first gate and the second gate and is located directly below a portion of the first gate and directly below a portion of the second gate. The N-type drain region is located in the N-type drift region. A P-type barrier region is located in the P-type substrate below the N-type drift region. The P-type barrier region has an overlapping portion overlapping the N-type drift region. There is at least one first opening in the overlapping portion.

Abstract: Disclosed is a power control system with zero voltage switching including a power controller, a rectification unit, a power unit, a transformer unit, a primary side switch unit, a current sensing unit, an auxiliary switch unit, an output unit, and a current sensing unit for implementing a function of flyback power conversion. The power controller has a power pin, a ground pin, a primary side driving pin, a voltage sensing pin, an auxiliary driving pin, and an auxiliary winding sensing pin, In particular, the auxiliary switch unit is controlled to influence an primary side winding through an auxiliary winding so as to reduce the drain voltage of the primary side switch unit. Further, the primary side switch unit is turned on when the drain voltage is decreased to the lowest value, thereby greatly reducing switching loss and increasing efficiency of power conversion.

Abstract: A multi-channel memory device includes N first memory blocks, a first redundancy memory block, and N first interface circuits. Each of the first interface circuits is coupled to two of the first memory blocks and the first redundancy memory block. The first interface circuits respectively select N first selected memory blocks in the first memory block and the first redundancy memory block according to a plurality of first selection signals, where N is a positive integer greater than 1.

Abstract: A media streaming device includes a power manager, a stream processor, and a voltage detector. The power manager receives a power signal from the media playback device to supply power to the stream processor. The stream processor provides media stream to the media playback device for playback. The voltage detector is electrically coupled to the stream processor and captures at least a part of the power supply current to the stream processor. The stream processor is configured to determine whether the power supply voltage remains stable. When the supply voltage remains stable, the stream processor operates in a first mode to provide media stream. When the power supply voltage is unstable, the stream processor operates in a second mode to provide media stream, and the power consumption of the stream processor in the second mode is lower than the power consumption in the first mode.

Abstract: A slim-type gas transportation device includes a slim-type gas pump and a slim-type valve structure. The slim-type valve structure includes a first thin plate, a valve frame, a valve plate and a second thin plate. The first thin plate has a hollow portion. The valve plate is disposed within an accommodation space of the valve frame. The valve plate includes a valve opening. The valve opening is not aligned with the hollow portion. The second thin plate includes a gas outlet surface, a pressure relief surface, a gas outlet groove, an outlet aperture, a pressure relief hole and a pressure relief trench. The outlet aperture is hollowed out from the gas outlet groove to the pressure relief surface and corresponding in position to the valve opening. The pressure relief hole is spaced apart from the gas outlet groove. The pressure relief trench is concavely formed from the pressure relief surface.

Abstract: System on chips, memory circuits, and method for data access, the memory circuits including a memory cell array and an input/output (I/O) connection interface coupled to the memory cell array, wherein the I/O connection interface is configured for coupling to an external signal line to directly receive a transistor-level operation signal from an external memory controller for accessing data in the memory cell array.

Abstract: At least two lighting modules are disposed on a printed circuit board (PCB). Each of the lighting modules includes a plurality of light emitting diode (LED) chips disposed in a non-rectangular array. Lenses are provided over the lighting modules. Each lens has a convex outer surface, and a chamber with a planar or concave inner surface facing a corresponding lighting module and disposed to cover the LED set within the chamber. A light projecting device includes a plurality of LED sets and a plurality of lenses. An orientation part couples each lighting module to the PCB at a non-zero angle.

Abstract: The present invention discloses a method of standby power supply including steps of: detecting a loading level; determining the loading level; entering a select mode; selecting a standby mode; entering a no-load mode, or a sleep mode, or a power-down mode; during the no-load mode, generating a no-load sustaining power, and returning back to detect the loading level when a preset condition is met; during the sleep mode, generating a sleep sustaining power, and returning back to detect the loading level when the preset condition is met; during the power-down mode, ceasing the power and entering a power-down recovery mode; and during the power-down recovery mode, returning back to detect the loading level when the preset condition is met. Therefore, the present invention implements power conversion for normal power supply, and particularly effectively controls the amount of power in the standby state, thereby greatly reducing power consumption and improving power saving.

Abstract: A voltage regulator includes a main driving stage circuit, a first pre-driving circuit, a plurality of auxiliary driving stage circuits, a second pre-driving circuit, and a comparison and decoding circuit. The main driving stage circuit provides a main driving current of an output voltage according to a first control signal. Each of the auxiliary driving stage circuits determines whether to provide an auxiliary driving current of the output voltage according to a second control signal. The second pre-driving circuit generates the second control signal according to an enable signal. The comparison and decoding circuit generates a simulated driving current and generates a load current according to a reference current and a counting code, compares the simulated driving current with the load current to generate a comparison result, and generates the enable signal by decoding the comparison result. The counting code is generated according to the comparison result.

Abstract: A testing circuit includes a command pad, a first circuit, a second circuit, a first latch, and a second latch. The command pad receives an operation command. The first integrated circuit performs a corresponding test operation according to the operation command and an internal selection signal. The second integrated circuit performs the corresponding test operation according to the operation command and an internal selection signal. The first latch provides the operation command to the first integrated circuit according to the internal selection signal. The second latch provides the operation command to the second integrated circuit according to the internal selection signal.

Abstract: Disclosed is a power control system of adaptive control of turn on time, including a primary side digital controller, a secondary side synchronization controller, a rectification unit, a power unit, a transformer unit, a primary side switch unit, a current sensing unit, a secondary side switch unit, and a secondary side output capacitor for implementing a function of flyback power conversion. The secondary side synchronization controller is intended to turn on or off the secondary side switch unit to achieve a synchronization function of rectification, and the primary side digital controller reduces a primary side drain-source voltage of the primary side switch unit and a secondary side drain-source voltage of the secondary side switch unit by reducing a current sensing limit used to compare with the current sensing signal. The power control system thus greatly improves stability and endurance of the overall operation.

Abstract: A low-dropout regulator including a first comparator, an edge trigger, a second comparator, a third comparator, and an output stage circuit is provided. The first comparator generates a first comparison signal according to a first reference signal and an output signal. The edge trigger outputs a trigger signal according to the first comparison signal, a second comparison signal, and a third comparison signal. The second comparator generates the second comparison signal according to the output signal and a second reference signal. The third comparator generates the third comparison signal according to the output signal and a third reference signal. The output stage circuit outputs the output signal according to the first comparison signal, the second comparison signal, and the third comparison signal. The output stage circuit includes a plurality of hysteresis controllers and a plurality of power transistors. Each hysteresis controller controls a conduction state of a corresponding power transistor.

Abstract: A voltage regulator includes a main driving stage circuit, a first pre-driving circuit, a plurality of auxiliary driving stage circuits, a second pre-driving circuit, and a comparison and decoding circuit. The main driving stage circuit provides a main driving current of an output voltage according to a first control signal. Each of the auxiliary driving stage circuits determines whether to provide an auxiliary driving current of the output voltage according to a second control signal. The second pre-driving circuit generates the second control signal according to an enable signal. The comparison and decoding circuit generates a simulated driving current and generates a load current according to a reference current and a counting code, compares the simulated driving current with the load current to generate a comparison result, and generates the enable signal by decoding the comparison result. The counting code is generated according to the comparison result.

Abstract: Disclosed is a variable-frequency power controller. The controller includes a power pin, a ground pin, a driving pin, a voltage sensing pin, and a loading voltage sensing pin, and is in collocation with a rectification unit, an inductor unit, a switch unit, an output unit, a voltage sensing unit, and a loading voltage sensing unit to implement a variable-frequency power control of power conversion. The controller performs one of the burst mode, valley switch mode, quasi-resonance (QR) mode, conduction mode, and peak loading mode based on a wide range of loading level. In particular, the loading level covered by the present invention includes the ultra-light, light, middle, full, and over-heavy loading, and the features of power saving, low switching loss, operation safety are thus achieved. Further, any over design employed to meet the wide range of loading level is prevented.

Abstract: Disclosed is a variable-frequency power controller. The controller includes a power pin, a ground pin, a driving pin, a voltage sensing pin, and a loading voltage sensing pin, and is in collocation with a rectification unit, an inductor unit, a switch unit, an output unit, a voltage sensing unit, and a loading voltage sensing unit to implement a variable-frequency power control of power conversion. The controller performs one of the burst mode, valley switch mode, quasi-resonance (QR) mode, conduction mode, and peak loading mode based on a wide range of loading level. In particular, the loading level covered by the present invention includes the ultra-light, light, middle, full, and over-heavy loading, and the features of power saving, low switching loss, operation safety are thus achieved. Further, any over design employed to meet the wide range of loading level is prevented.

Abstract: Disclosed is a method of controlling a time parameter performed by a power controller having a power pin, a ground pin, a driving pin, a time parameter selecting pin, a feedback pin, and a current sensing pin. The power controller is in collocation with a rectification unit, a transformer, a switch unit, a power output unit, and a feedback unit. A Pulse Width Modulation (PWM) frequency of a driving signal, an Over-Voltage Protection (OVP) delay time, and an Under-Voltage Protection (UVP) delay time are preset in the power controller. An external time parameter selecting signal is received through the time parameter selecting pin to dynamically update the PWM frequency, the OVP delay time, or the UVP delay time, thereby greatly increasing efficiency of power conversion and avoiding malfunction of OVP or UVP.