Patents by Inventor Chih-hao Chen

Chih-hao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210066121
    Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over a target layer, forming a plurality of spacers over the first mask layer, and forming a second mask layer over the plurality of spacers and patterning the second mask layer to form a first opening, where in a plan view a major axis of the opening extends in a direction that is perpendicular to a major axis of a spacer of the plurality of spacers. The method also includes depositing a sacrificial material in the opening, patterning the sacrificial material, etching the first mask layer using the plurality of spacers and the patterned sacrificial material, etching the target layer using the etched first mask layer to form second openings in the target layer, and filling the second openings in the target layer with a conductive material.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 4, 2021
    Inventors: Tai-Yen Peng, Wen-Yen Chen, Chih-Hao Chen
  • Publication number: 20210066294
    Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.
    Type: Application
    Filed: July 17, 2020
    Publication date: March 4, 2021
    Inventors: Jui-Chien Huang, Shih-Cheng Chen, Chih-Hao Wang, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Lo-Heng Chang, Shi Ning Ju, Guan-Lin Chen
  • Publication number: 20210066137
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.
    Type: Application
    Filed: July 10, 2020
    Publication date: March 4, 2021
    Inventors: Chung-Wei Hsu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Hou-Yu Chen, Ching-Wei Tsai, Chih-Hao Wang, Lung-Kun Chu, Mao-Lin Huang, Jia-Ni Yu
  • Publication number: 20210066269
    Abstract: Semiconductor packages are provided. The semiconductor package includes a first redistribution layer structure, a photonic integrated circuit, an electronic integrated circuit, a waveguide and a memory. The photonic integrated circuit is disposed over and electrically connected to the first redistribution layer structure, and includes an optical transceiver and an optical coupler. The electronic integrated circuit is disposed over and electrically connected to the first redistribution layer structure. The waveguide is optically coupled to the optical coupler. The memory is electrically connected to the electronic integrated circuit.
    Type: Application
    Filed: May 5, 2020
    Publication date: March 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chieh Yang, Ching-Hua Hsieh, Chih-Wei Lin, Yu-Hao Chen
  • Publication number: 20210055616
    Abstract: An electronic device is provided. The electronic device includes a substrate, a driving circuit disposed on the substrate, an active region disposed on the substrate, and a wiring group disposed on the substrate and between the driving circuit and the active area. The wiring group includes a first conductive line and a second conductive line. The first conductive line has a first section and a second section electrically connected to the first section and disposed between the first section and the active region. The second conductive line includes a third section and a fourth section electrically connected to the third section and disposed between the third section and the active region. The first section and the second section are not the same layer. The first section and the fourth section are the same layer. The second section and the third section are the same layer.
    Type: Application
    Filed: July 29, 2020
    Publication date: February 25, 2021
    Inventors: Chih-Hao HSU, Chia-Min YEH, Hsieh-Li CHOU, Cheng-Tso CHEN, Hui-Min HUANG, Li-Wei SUNG, Yu-Ti HUANG
  • Publication number: 20210057297
    Abstract: A method for forming a package structure is provided. The method for forming a package structure includes bonding a package component to a first surface of a substrate through a plurality of first connectors. The package component includes an interposer, a first semiconductor die and a second semiconductor die over the interposer. The method for forming a package structure also includes forming a dam structure over the first surface of the substrate. The dam structure is around and separated from the package component. The method for forming a package structure further includes forming an underfill layer between the dam structure and the package component, and removing the dam structure after the underfill layer is formed.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Inventors: Chih-Hao CHEN, Chih-Chien PAN, Li-Hui CHENG, Chin-Fu KAO, Szu-Wei LU
  • Patent number: 10930794
    Abstract: A method of fabricating a semiconductor device includes forming a fin extruding from a substrate, the fin having a plurality of sacrificial layers and a plurality of channel layers, wherein the sacrificial layers and the channel layers are alternately arranged; removing a portion of the sacrificial layers from a channel region of the fin; depositing a spacer material in areas from which the portion of the sacrificial layers have been removed; selectively removing a portion of the spacer material, thereby exposing the channel layers in the channel region of the fin, wherein other portions of the spacer material remain as a spacer feature; and forming a gate structure engaging the exposed channel layers.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Guan-Lin Chen, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20210050281
    Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.
    Type: Application
    Filed: October 19, 2020
    Publication date: February 18, 2021
    Inventors: Chih-Horng Chang, Jie-Cheng Deng, Tin-Hao Kuo, Ying-Yu Chen
  • Patent number: 10921981
    Abstract: An electronic device includes a keyboard module, a silicone film, a light-emitting module, and a touch module. The keyboard module has a plurality of buttons and a point stick. The silicone film has a virtual touch region. The light-emitting module is configured below the silicone film and corresponds to the virtual touch region. The light-emitting module includes a first light-emitting unit and a second light-emitting unit. The touch module is configured below the silicone film and corresponds to the virtual touch region. The touch module includes a control chip and a sensing layer. The point stick, the first light-emitting unit, the second light-emitting unit, and the sensing layer are electrically connected to the control chip, respectively.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: February 16, 2021
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Meng-Huan Tsai, Yen-Hua Hsiao, Yun-Tung Pai, Chih-Yuan Lee, Chien-Hao Ho, Chia-Hua Wu, Kung-Ju Chen, Chia-Chi Lin, Chia-Chi Sun
  • Patent number: 10917774
    Abstract: A method applied to a wireless Bluetooth audio communication system includes: providing an audio gateway of a first piconet to communicate with a master device in the first piconet and to transmit at least one packet of audio stream to the master device and a slave device; employing a first transceiver as the master device to receive the at least one packet of the audio stream from the audio gateway; and, employing a second transceiver as the slave device to receive the at least one packet of the audio stream from the audio gateway and to acknowledge the first transceiver whether the second transceiver has successfully received the at least one packet of the audio stream from the audio gateway.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: February 9, 2021
    Assignee: Audiowise Technology Inc.
    Inventors: Kuang-Hu Huang, Wei-Chung Peng, Jeng-Hong Chen, Pete Hsinhsiang Liu, De-Hao Tseng, Jing-Syuan Jia, Chih-Wei Sung, I-Ken Ho
  • Patent number: 10916517
    Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: February 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih Wei Bih, Sheng-Wei Yeh, Yen-Yu Chen, Wen-Hao Cheng, Chih-Wei Lin, Chun-Chih Lin
  • Publication number: 20210035906
    Abstract: The present disclosure provides a method of forming a semiconductor device structure. The method includes forming a trench in a dielectric layer on a semiconductor substrate; forming a bottom metal feature of a first metal in a lower portion of the trench by a selective deposition; depositing a barrier layer in an upper portion of the trench, the barrier layer directly contacting both a top surface of the bottom metal feature and sidewalls of the dielectric layer; and forming a top metal feature of a second metal on the barrier layer, filling in the upper portion of the trench, wherein the second metal is different from the first metal in composition.
    Type: Application
    Filed: May 15, 2020
    Publication date: February 4, 2021
    Inventors: Chun-Yuan Chen, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20210035969
    Abstract: A high-voltage circuitry device is provided. The high-voltage circuitry device includes a high-voltage transistor, a protection component and a feedback component. The high-voltage transistor has a gate, a drain and a source. The protection component is coupled between the source of the high-voltage transistor and the ground. When a current corresponding to an electrostatic discharge (ESD) event flows through the drain of the high-voltage transistor, the current flows from the drain of the high-voltage transistor to the ground through the high-voltage transistor and the protection component. The feedback component is coupled between the protection component, the ground and the gate of the high-voltage transistor. When the ESD event occurs, the feedback component enables the high-voltage transistor to stay on a turned-on state to pass the current.
    Type: Application
    Filed: November 18, 2019
    Publication date: February 4, 2021
    Inventors: Yi-Hao CHEN, Tsu-Yi WU, Chih-Hsun LU, Po-An CHEN, Chun-Chieh LIU
  • Publication number: 20210033915
    Abstract: A display panel includes a first substrate, an electrode layer, and a display medium layer. The electrode layer is disposed on the first substrate. The display medium layer is disposed on the electrode layer and includes a filler and liquid crystal capsules. The liquid crystal capsules are distributed in the filler, and the filler has a birefringence difference ?n in a range from 0.02 to 0.175.
    Type: Application
    Filed: April 6, 2020
    Publication date: February 4, 2021
    Inventors: Liang-Yin HUANG, Chih-Hao CHEN, Min-Zi HONG, Seok-Lyul LEE
  • Publication number: 20210035938
    Abstract: The present disclosure relates to an integrated chip structure having a first copper pillar disposed over a metal pad of an interposer substrate. The first copper pillar has a sidewall defining a recess. A nickel layer is disposed over the first copper pillar and a solder layer is disposed over the first copper pillar and the nickel layer. The solder layer continuously extends from directly over the first copper pillar to within the recess. A second copper layer is disposed between the solder layer and a second substrate.
    Type: Application
    Filed: October 21, 2020
    Publication date: February 4, 2021
    Inventors: Chih-Horng Chang, Tin-Hao Kuo, Chen-Shien Chen, Yen-Liang Lin
  • Patent number: 10908485
    Abstract: An optical element adjusting device includes an outer frame; an inner frame framing an optical element and disposed in the outer frame; a first adjusting structure, including a first adjusting part connected to one of two opposite outer sides of the inner frame, and movably disposed through the outer frame; and a second adjusting structure, including a through channel formed in the outer frame and having connected first and second sub-channels, a second adjusting part connected to the other outer side and movably disposed in the first sub-channel, an adjusting element movably disposed in the second sub-channel, and a rolling element disposed in the through channel and between the second adjusting part and the adjusting element. The position of the optical element can be adjusted by rotating the rolling element through the adjusting element. An electronic device including the optical element adjusting device is also provided.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: February 2, 2021
    Assignee: Coretronic Corporation
    Inventors: Chih-Hao Wang, Chia-Jun Chen
  • Publication number: 20210020625
    Abstract: A transient voltage suppression device including a substrate of a first conductivity type, a first well of a second conductivity type, a first anode, a first cathode, and a first trigger node is provided. The first well is disposed in the substrate. The first anode is disposed in the substrate outside the first well and includes a second doped region of the second conductivity type and a third doped region of the first conductivity type disposed between the second doped region and the first doped region. The first trigger node is disposed between the first anode and the first cathode, and includes a fourth region of the first conductivity type disposed in the substrate and a fifth doped region of the second conductivity type at least partially disposed in the first well and disposed between the fourth doped region and the third doped region.
    Type: Application
    Filed: June 24, 2020
    Publication date: January 21, 2021
    Applicant: uPI Semiconductor Corp.
    Inventors: Cheng-Chi Lin, Chih-Hao Chen
  • Publication number: 20210020524
    Abstract: A method includes forming an epitaxy semiconductor layer over a semiconductor substrate, and etching the epitaxy semiconductor layer and the semiconductor substrate to form a semiconductor strip, which includes an upper portion acting as a mandrel, and a lower portion under the mandrel. The upper portion is a remaining portion of the epitaxy semiconductor layer, and the lower portion is a remaining portion of the semiconductor substrate. The method further includes growing a first semiconductor fin starting from a first sidewall of the mandrel, growing a second semiconductor fin starting from a second sidewall of the mandrel. The first sidewall and the second sidewall are opposite sidewalls of the mandrel. A first transistor is formed based on the first semiconductor fin. A second transistor is formed based on the second semiconductor fin.
    Type: Application
    Filed: July 18, 2019
    Publication date: January 21, 2021
    Inventors: Pei-Hsun Wang, Shih-Cheng Chen, Chun-Hsiung Lin, Chih-Hao Wang
  • Publication number: 20200411329
    Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.
    Type: Application
    Filed: September 12, 2020
    Publication date: December 31, 2020
    Inventors: TUNG-KAI CHEN, CHING-HSIANG TSAI, KAO-FENG LIAO, CHIH-CHIEH CHANG, CHUN-HAO KUNG, FANG-I CHIH, HSIN-YING HO, CHIA-JUNG HSU, HUI-CHI HUANG, KEI-WEI CHEN
  • Patent number: 10879070
    Abstract: An embodiment is a method of fabricating a semiconductor structure. The method includes utilize uses of a multi-layer structure disposed on a pattern defining layer. In some embodiments, a method of fabricating a semiconductor structure includes forming a first multi-layer structure on a pattern defining layer disposed on a film stack on a substrate, patterning the first multi-layer structure to form an aperture in the first multi-layer structure, forming a first cut opening in the pattern defining layer through the aperture defined by the first multi-layer structure, and forming a second multi-layer structure on the pattern defining layer, a portion of the second multi-layer structure being disposed in the first cut opening.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiann-Horng Lin, Yi-Chang Lee, Che-Kang Chu, Chih-Hao Chen