Patents by Inventor Chih-hao Chen

Chih-hao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250149401
    Abstract: A manufacturing method of a package structure includes: forming a first package component, where the first package component includes a first insulating encapsulation laterally covering semiconductor dies and a redistribution structure formed on the first insulating encapsulation and the semiconductor dies; coupling the first package component to a second package component; forming an underfill layer between the first and second package component, where the underfill layer extends to cover a sidewall of the first package component; forming a metallic layer on opposing surfaces of the semiconductor dies and the first insulating encapsulation by using a jig, where a window of the jig accessibly exposes the opposing surfaces of the semiconductor dies and the first insulating encapsulation, and a peripheral region of the opposing surface of the first insulating encapsulation is shielded by the jig.
    Type: Application
    Filed: January 9, 2025
    Publication date: May 8, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Po-Yuan Cheng, Pu Wang, Li-Hui Cheng
  • Publication number: 20250096062
    Abstract: A package structure includes a package substrate, an interposer module on the package substrate, a thermal interface material (TIM) layer on the interposer module, and a package lid on the TIM layer, including a package lid foot portion attached to the package substrate, a package lid plate portion connected to the package lid foot portion, and a plurality of fins extending from the package lid plate portion into the TIM layer over the interposer module.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 20, 2025
    Inventors: Ping-Yin Hsieh, Chih-Hao Chen, Li-Hui Cheng, Ying-Ching Shih
  • Patent number: 12243966
    Abstract: A light-emitting device comprises a semiconductor stack emitting a light with a peak wavelength ?; and a light field adjustment layer formed on the semiconductor stack, wherein the light field adjustment layer comprises a plurality of first layers and a plurality of second layers alternately stacked on top of each other, the plurality of first layers each comprises a first optical thickness, and the plurality of second layers each comprises a second optical thickness.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: March 4, 2025
    Assignee: EPISTAR CORPORATION
    Inventors: Heng-Ying Cho, Li-Yu Shen, Chih-Hao Chen, Keng-Lin Chuang
  • Publication number: 20250069989
    Abstract: A semiconductor device includes a FEOL structure and a BEOL structure. The BEOL structure is formed over the FEOL structure and includes a conductive layer, an etching stop layer (ESL) structure, a through via and a barrier layer. The ESL structure is formed over the conductive layer and has a first recess and a lateral surface. The through via passes through the ESL structure to form the first recess and the lateral surface. The barrier layer covers the lateral surface and the first recess. The first recess is recessed with respect to the lateral surface, and the first recess has a first depth ranging between 1 nm and 7 nm.
    Type: Application
    Filed: August 25, 2023
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Chih HUANG, Li-An SUN, Chih-Hao CHEN, Chung-Chuan HUANG
  • Patent number: 12230744
    Abstract: A light-emitting device includes a substrate including a top surface, a first side surface and a second side surface, wherein the first side surface and the second side surface of the substrate are respectively connected to two opposite sides of the top surface of the substrate; a semiconductor stack formed on the top surface of the substrate, the semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first electrode pad formed adjacent to a first edge of the light-emitting device; and a second electrode pad formed adjacent to a second edge of the light-emitting device, wherein in a top view of the light-emitting device, the first edge and the second edge are formed on different sides or opposite sides of the light-emitting device, the first semiconductor layer adjacent to the first edge includes a first sidewall directly connected to the first side surface of the substrate,
    Type: Grant
    Filed: September 20, 2023
    Date of Patent: February 18, 2025
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Cheng-Lin Lu, Chih-Hao Chen, Chi-Shiang Hsu, I-Lun Ma, Meng-Hsiang Hong, Hsin-Ying Wang, Kuo-Ching Hung, Yi-Hung Lin
  • Publication number: 20250054824
    Abstract: A package structure including a packaging substrate, a semiconductor device, passive components, a lid, and a dam structure is provided. The semiconductor device is disposed on and electrically connected to the packaging substrate. The passive components are disposed on the packaging substrate, wherein the semiconductor device is surrounded by the passive components. The lid is disposed on the packaging substrate, and the lid covers the semiconductor device and the passive components. The dam structure is disposed between the packaging substrate and the lid, wherein the dam structure covers the passive components and laterally encloses the semiconductor device.
    Type: Application
    Filed: August 8, 2023
    Publication date: February 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi Wen Huang, Chih-Hao Chen, Ping-Yin Hsieh, Yi-Huan Liao, Li-Hui Cheng
  • Patent number: 12224224
    Abstract: A package structure includes first and second package components, an underfill layer disposed between the first and second package components, and a metallic layer. The first package component includes semiconductor dies, a first insulating encapsulation laterally encapsulating the semiconductor dies, and a redistribution structure underlying first surfaces of the semiconductor dies and the first insulating encapsulation. The second package component underlying the first package component is electrically coupled to the semiconductor dies through the redistribution structure. The underfill layer extends to cover a sidewall of the first package component, the metallic layer overlying second surfaces of the semiconductor dies and the first insulating encapsulation, and a peripheral region of the second surface of the first insulating encapsulation is accessibly exposed by the metallic layer, where the first surfaces are opposite to the second surfaces.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: February 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Po-Yuan Cheng, Pu Wang, Li-Hui Cheng
  • Patent number: 12218282
    Abstract: A light-emitting device includes a first semiconductor layer; a semiconductor pillar formed on the first semiconductor layer, including a second semiconductor layer and an active layer, wherein the semiconductor pillar comprises an outmost periphery; a first contact layer formed on the first semiconductor layer and including a first contact portion and a first extending portion, wherein the first extending portion continuously surrounds an entirety of the outmost periphery of the semiconductor pillar and the first contact portion; a second contact layer formed on the second semiconductor layer; a first insulating layer including multiple first openings exposing the first contact layer and multiple second openings exposing the second contact layer; a first electrode contact layer connected to the first contact portion through the multiple first openings and covering all of the first contact layer; a second electrode contact layer connected to the second contact layer through the multiple second openings.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: February 4, 2025
    Assignee: EPISTAR CORPORATION
    Inventors: Aurelien Gauthier-Brun, Chao-Hsing Chen, Chang-Tai Hsaio, Chih-Hao Chen, Chi-Shiang Hsu, Jia-Kuen Wang, Yung-Hsiang Lin
  • Patent number: 12211818
    Abstract: A jig for manufacturing a semiconductor package includes a bottom piece and an upper piece. The bottom piece includes a base, a support plate, and at least one elastic connector. The support plate is located in a central region of the base. The at least one elastic connector is interposed between the support plate and the base. The upper piece includes a cap and outer flanges. The cap overlays the support plate when the upper piece is disposed on the bottom piece. The outer flanges are disposed at edges of the cap, connected with the cap. The outer flanges contact the base of the bottom piece when the upper piece is disposed on the bottom piece. The cap includes an opening which is a through hole. When the upper piece is disposed on the bottom piece, a vertical projection of the opening falls entirely on the support plate.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chih-Chien Pan, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 12176261
    Abstract: A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: December 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 12170236
    Abstract: A method for forming a package structure is provided. The method includes bonding a package component to a substrate through a plurality of first connectors. The package component comprises a first semiconductor die and a second semiconductor die. The method also includes forming a dam structure over the substrate and surrounding the first connectors. A top surface of the dam structure is lower than a bottom surface of the package component. The method further includes filling an underfill layer in a space between the dam structure and the first connectors. In addition, the method includes removing the dam structure after the underfill layer is formed.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: December 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Chih-Hao Chen, Chih-Chien Pan, Li-Hui Cheng, Chin-Fu Kao, Szu-Wei Lu
  • Publication number: 20240395508
    Abstract: A semiconductor manufacturing apparatus for performing a process is disclosed. An apparatus includes a chamber configured to receive a wafer for an etching process; a conductive focus ring disposed within the chamber and configured to focus an electric field to control an etch direction of the etching process; and an insulative cover ring disposed within the chamber, wherein the insulative cover ring is configured to modify the electric field, wherein the insulative cover ring has an inner annular insulative portion and outer annular insulative portion, and wherein a gap is defined between the inner annular insulative portion and the outer annular insulative portion.
    Type: Application
    Filed: May 25, 2023
    Publication date: November 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chung Chuan Huang, Yi-Tsang Hsieh, Yu-Chi Lin, Cha-Hsin Chao, Che-En Tsai
  • Publication number: 20240395727
    Abstract: Semiconductor devices and methods of manufacture are provided, in which an adhesive is removed from a semiconductor die embedded within an encapsulant, and an interface material is utilized to remove heat from the semiconductor device. The removal of the adhesive leaves behind a recess adjacent to a sidewall of the semiconductor, and the recess is filled.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Chih-Hao Chen, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 12155019
    Abstract: A light-emitting device comprises a substrate comprising a top surface and a sidewall; a semiconductor stack formed on the top surface of the substrate comprising a first semiconductor layer, an active layer and a second semiconductor layer; a dicing street surrounding the semiconductor stack and exposing the top surface of the substrate; a protective layer covering the semiconductor stack and the dicing street; a reflective layer comprising a Distributed Bragg Reflector structure and covering the protective layer; and a cap layer covering the reflective layer, wherein the reflective layer comprises an uneven portion adjacent to the sidewall of the substrate, and the uneven portion comprises an uneven thickness.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: November 26, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Hsin-Ying Wang, Chih-Hao Chen, Chien-Chih Liao, Chao-Hsing Chen, Wu-Tsung Lo, Tsun-Kai Ko, Chen Ou
  • Publication number: 20240387372
    Abstract: A method includes forming a first etch stop layer (ESL) over a conductive feature, forming a first dielectric layer on the first ESL, forming a second ESL on the first dielectric layer, forming a second dielectric layer on the second ESL, forming a trench in the second dielectric layer, forming a first opening in a bottom surface of the trench extending through the second dielectric layer, and forming a second opening in a bottom surface of the first opening. The second opening extends through the first dielectric layer and the first ESL. The second opening exposes a top surface of the conductive feature. The method further includes widening the first opening to a second width, filling the trench with a conductive material to form a conductive line, and filling the second opening and the first opening with the conductive material to form a conductive via.
    Type: Application
    Filed: July 28, 2024
    Publication date: November 21, 2024
    Inventors: Yen-Chih Huang, Li-An Sun, Che-En Tsai, Yu-Lin Chiang, Chung Chuan Huang, Chih-Hao Chen
  • Publication number: 20240384431
    Abstract: A method for colorizing an aluminum-containing object includes the steps of: (a) subjecting the aluminum-containing object to a first pretreatment, so as to remove contaminants from a surface thereof; and (b) subjecting the pretreated aluminum-containing object obtained in step (a) to an anodizing treatment which is accomplished by applying N cycles of periodic current signals, thereby forming an aluminum oxide film with a plurality of nanopores on the surface of the aluminum-containing object. In step (b), each cycle of the periodic current signals includes a first to fourth predetermined time periods. A colorized aluminum-containing object prepared by the aforesaid method is also provided.
    Type: Application
    Filed: May 16, 2024
    Publication date: November 21, 2024
    Applicant: Jabil Circuit (Singapore) Pte. Ltd.
    Inventors: Yi-Chung Su, Pen-Yi Liao, Chih-Hao Chen, Wen-Chia Tsai
  • Publication number: 20240387446
    Abstract: A jig for manufacturing a semiconductor package includes a bottom piece and an upper piece. The bottom piece includes a base, a support plate, and at least one elastic connector. The support plate is located in a central region of the base. The at least one elastic connector is interposed between the support plate and the base. The upper piece includes a cap and outer flanges. The cap overlays the support plate when the upper piece is disposed on the bottom piece. The outer flanges are disposed at edges of the cap, connected with the cap. The outer flanges contact the base of the bottom piece when the upper piece is disposed on the bottom piece. The cap includes an opening which is a through hole. When the upper piece is disposed on the bottom piece, a vertical projection of the opening falls entirely on the support plate.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chih-Chien Pan, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Publication number: 20240371725
    Abstract: A method of forming a semiconductor structure includes: attaching a semiconductor device to a first surface of a substrate; placing a thermal interface material (TIM) film over a first side of the semiconductor device distal from the substrate, where the TIM film is pre-formed before the placing, where after the placing, a peripheral portion of the TIM film extends laterally beyond sidewalls of the semiconductor device; and attaching a lid to the first surface of the substrate to form an enclosed space between the lid and the substrate, where after attaching the lid, the semiconductor device and the TIM film are disposed in the enclosed space, where a first side of the TIM film distal from the substrate contacts the lid.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventors: Chih-Hao Chen, Hung-Yu Chen, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Publication number: 20240363365
    Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Hui Cheng, Szu-Wei Lu, Ping-Yin Hsieh, Chih-Hao Chen
  • Patent number: 12132004
    Abstract: Semiconductor devices and methods of manufacture are provided, in which an adhesive is removed from a semiconductor die embedded within an encapsulant, and an interface material is utilized to remove heat from the semiconductor device. The removal of the adhesive leaves behind a recess adjacent to a sidewall of the semiconductor, and the recess is filled.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hao Chen, Pu Wang, Li-Hui Cheng, Szu-Wei Lu