Abstract: A device includes an active region, a gate structure, a source/drain epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The source/drain epitaxial structure is over the active region and adjacent the gate structure. The epitaxial layer is over the source/drain epitaxial structure. The metal alloy layer is over the epitaxial layer. The contact is over the metal alloy layer. The contact etch stop layer lines sidewalls of the source/drain epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.

Abstract: The present disclosure provides a connecting device and a lamp system. The connecting device is used to connect multiple lamps to form the lamp system. The connecting device includes a connecting element, a cover, and a shell. The cover is mounted on the connecting element and includes at least two first assembling members. The shell is detachably mounted on the cover. The shell includes a side wall, an opening, multiple gateways, and at least two second assembling members. The side wall surrounds a space. The opening and the gateways all are formed on a top of the side wall and communicate with the space. A portion of each of the lamps is received in one of the gateways. The second assembling members are disposed on the side wall and face each other in a radial line of the shell, and respectively engage with the first assembling members.

Abstract: A light emitting diode device includes a substrate, a conductive via, first and second conductive pads, a driving chip, a flat layer, a redistribution layer, a light emitting diode, and an encapsulating layer. The substrate has a first surface and a second surface opposite thereto. The conductive via penetrates from the first surface to the second surface. The first and second conductive pads are respectively disposed on the first and second surface and in contact with the conductive via. The driving chip is disposed on the first surface. The flat layer is disposed over the first surface and covers the driving chip and the first conductive pad. The redistribution layer is disposed on the flat layer and electrically connects to the driving chip. The light emitting diode is flip-chip bonded to the redistribution layer. The encapsulating layer covers the redistribution layer and the light emitting diode.

Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a first source/drain region disposed under a well portion, a second source/drain region disposed adjacent the first source/drain region, a dielectric material disposed between the first and second source/drain regions, and a conductive contact having a first portion disposed under the first source/drain region and a second portion disposed adjacent the first source/drain region. The second portion is disposed in the dielectric material. The structure further includes a conductive feature disposed in the dielectric material, and the conductive feature is electrically connected to the conductive contact. The conductive feature has a top surface that is substantially coplanar with a top surface of the well portion.

Abstract: A semiconductor device structure is provided. The semiconductor device has a first dielectric wall between an n-type source/drain region and a p-type source/drain region to physically and electrically isolate the n-type source/drain region and the p-type source/drain region from each other. A second dielectric wall is formed between a first channel region connected to the n-type source/drain region and a second channel region connected to the p-type source/drain region. A contact is formed to physically and electrically connect the n-type source/drain region with the p-type source/drain region, wherein the contact extends over the first dielectric wall. The first electric wall has a gradually decreasing width W5 towards a tip of the dielectric wall from a top contact position between the first dielectric wall and either the n-type source/drain region or the p-type source/drain region.

Abstract: A mending method for a display includes the steps of making a display device light to make a plurality of light emitting positions thereof shine, searching out a plurality of defect positions among the light emitting positions, providing a transferring device having a transferring surface with a plurality of miniature light emitting elements positioned correspondingly to the light emitting positions, planning a mending procedure which includes in the area the transferring surface corresponds to, choosing in chief the largest number of defect positions able to be mended at a single time according to the positions of the miniature light emitting elements and then in the area the transferring surface corresponds to, planning the rest of the defect positions according to the rest of the miniature light emitting elements, and according to the mending procedure, moving the transferring device to weld the miniature light emitting elements at the defect positions.

Abstract: The present disclosure is directed to techniques of zone-based target control in chemical mechanical polishing of wafers. Multiple zones are identified on a surface of a wafer. The CMP target is achieved on each zone in a sequence of CMP processes. Each CMP process in the sequence achieves the CMP target for only one zone, using a CMP process selective to other zones.

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Abstract: A fastener is adapted for assembling a first housing to a second housing. The first housing is provided with a protruding portion and a buckling portion, and the second housing has a first surface, a second surface, and a through hole. The fastener includes a first portion, at least one connecting portion, at least two elastic portions, and a second portion. The first portion movably abuts against the first surface and has a first opening. The connecting portion is accommodated in the through hole. One end of the connecting portion is connected to the first portion. The connecting portion is spaced apart from an inner edge of the second housing by a gap. The two elastic portions inclinedly extend into the first opening. The second portion movably abuts against the second surface and is disposed at the another end of the connecting portion.

Abstract: A display device includes a plurality of sub-pixels. The sub-pixels include a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first light emitting element and a first control circuit. The first control circuit is configured to provide a first driving current to the first light emitting element. The second sub-pixel includes a second light emitting element and a second control circuit. The second control circuit is configured to provide a second driving current to the second light emitting element. The first control circuit and the second control circuit are configured to differently control pulse amplitude of the first driving current and pulse amplitude of the second driving current, such that both of the first light emitting element and the second light emitting element emit at a target wavelength or a color point range (e.g. +/?1.5˜2 nm).

Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.

Abstract: The light emitting diode packaging structure includes a flexible substrate, a first adhesive layer, micro light emitting elements, a conductive pad, a redistribution layer, and an electrode pad. The first adhesive layer is disposed on the flexible substrate. The micro light emitting elements are disposed on the first adhesive layer and have a first surface facing to the first adhesive layer and an opposing second surface. The micro light emitting elements include a red micro light emitting element, a blue micro light emitting element, and a green micro light emitting element. The conductive pad is disposed on the second surface of the micro light emitting element. The redistribution layer covers the micro light emitting elements and the conductive pad. The electrode pad is disposed on the redistribution layer and is electrically connected to the circuit layer. A thickness of the flexible substrate is less than 100 um.

Abstract: A semiconductor structure includes a first channel layer and a first barrier layer on the first channel layer. The first channel layer has a first potential well adjacent to the interface between the first channel layer and the first barrier layer. The semiconductor structure further includes a second channel layer on the first barrier layer, a second barrier layer on the second channel layer, and an intermediate layer between the second channel layer and the second barrier layer. The second channel layer has a second potential well adjacent to the interface between the second channel layer and the intermediate layer. The intermediate layer has a greater energy gap than either the first barrier layer or the second barrier layer. The energy gap of the first barrier layer is no less than the energy gap of the second barrier layer.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials.

Abstract: The present disclosure relates to a semiconductor device having a backside source/drain contact, and method for forming the device. The semiconductor device includes a source/drain feature having a top surface and a bottom surface, a first silicide layer formed in contact with the top surface of the source/drain feature, a first conductive feature formed on the first silicide layer, and a second conductive feature having a body portion and a first sidewall portion extending from the body portion, wherein the body portion is below the bottom surface of the source/drain feature, and the first sidewall portion is in contact with the first conductive feature.

Abstract: A micro-electro-mechanical system (MEMS) microphone is provided. The MEMS microphone includes a substrate, a diaphragm, a backplate and a first protrusion. The substrate has an opening portion. The diaphragm is disposed on one side of the substrate and extends across the opening portion of the substrate. The backplate includes a plurality of acoustic holes. The backplate is disposed on one side of the diaphragm. An air gap is formed between the backplate and the diaphragm. The first protrusion extends from the backplate towards the air gap.

Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.

Abstract: A semiconductor device includes a first dielectric layer, a stack of semiconductor layers disposed over the first dielectric layer, a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction, and a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure. The dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction. The isolation structure includes a second dielectric layer extending through the gate structure and the first dielectric layer, and a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.

Abstract: A device includes: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures, the gate structure extending in a first direction; a source/drain region abutting the gate structure and the stack in a second direction transverse the first direction; a contact structure on the source/drain region; a backside conductive trace under the stack, the backside conductive trace extending in the second direction; a first through via that extends vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure that abuts the first through via in the second direction.