Patents by Inventor Chih-hao Chen
Chih-hao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240014352Abstract: A light-emitting device includes a substrate including a top surface, a first side surface and a second side surface, wherein the first side surface and the second side surface of the substrate are respectively connected to two opposite sides of the top surface of the substrate; a semiconductor stack formed on the top surface of the substrate, the semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first electrode pad formed adjacent to a first edge of the light-emitting device; and a second electrode pad formed adjacent to a second edge of the light-emitting device, wherein in a top view of the light-emitting device, the first edge and the second edge are formed on different sides or opposite sides of the light-emitting device, the first semiconductor layer adjacent to the first edge includes a first sidewall directly connected to the first side surface of the substrate,Type: ApplicationFiled: September 20, 2023Publication date: January 11, 2024Inventors: Chao-Hsing CHEN, Cheng-Lin LU, Chih-Hao CHEN, Chi-Shiang HSU, I-Lun MA, Meng-Hsiang HONG, Hsin-Ying WANG, Kuo-Ching HUNG, Yi-Hung LIN
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Patent number: 11869822Abstract: A semiconductor package includes a redistribution structure, a plurality of semiconductor devices, and a plurality of heat dissipation films. The plurality of semiconductor devices mounted on the redistribution structure. The plurality of heat dissipation films are respectively disposed on and jointly covering upper surfaces of the plurality of semiconductor devices. A plurality of trenches are respectively extended between each two of the plurality of heat dissipations and extended between each two of the plurality of semiconductor devices.Type: GrantFiled: July 23, 2021Date of Patent: January 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Po-Yuan Cheng, Pu Wang, Li-Hui Cheng
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Publication number: 20230395765Abstract: A light-emitting device comprises a substrate comprising a top surface and a sidewall; a semiconductor stack formed on the top surface of the substrate comprising a first semiconductor layer, an active layer and a second semiconductor layer; a dicing street surrounding the semiconductor stack and exposing the top surface of the substrate; a protective layer covering the semiconductor stack and the dicing street; a reflective layer comprising a Distributed Bragg Reflector structure and covering the protective layer; and a cap layer covering the reflective layer, wherein the reflective layer comprises an uneven portion adjacent to the sidewall of the substrate, and the uneven portion comprises an uneven thickness.Type: ApplicationFiled: August 3, 2023Publication date: December 7, 2023Inventors: Hsin-Ying WANG, Chih-Hao CHEN, Chien-Chih LIAO, Chao-Hsing CHEN, Wu-Tsung LO, Tsun-Kai KO, Chen OU
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Patent number: 11830821Abstract: Semiconductor devices and methods of manufacture are provided, in which an adhesive is removed from a semiconductor die embedded within an encapsulant, and an interface material is utilized to remove heat from the semiconductor device. The removal of the adhesive leaves behind a recess adjacent to a sidewall of the semiconductor, and the recess is filled.Type: GrantFiled: January 15, 2021Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hao Chen, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
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Publication number: 20230369283Abstract: A jig for manufacturing a semiconductor package includes a bottom piece and an upper piece. The bottom piece includes a base, a support plate, and at least one elastic connector. The support plate is located in a central region of the base. The at least one elastic connector is interposed between the support plate and the base. The upper piece includes a cap and outer flanges. The cap overlays the support plate when the upper piece is disposed on the bottom piece. The outer flanges are disposed at edges of the cap, connected with the cap. The outer flanges contact the base of the bottom piece when the upper piece is disposed on the bottom piece. The cap includes an opening which is a through hole. When the upper piece is disposed on the bottom piece, a vertical projection of the opening falls entirely on the support plate.Type: ApplicationFiled: July 26, 2023Publication date: November 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Chih-Chien Pan, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
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Publication number: 20230360995Abstract: A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer.Type: ApplicationFiled: July 21, 2023Publication date: November 9, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
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Patent number: 11804468Abstract: A jig for manufacturing a semiconductor package includes a bottom piece and an upper piece. The bottom piece includes a base, a support plate, and at least one elastic connector. The support plate is located in a central region of the base. The at least one elastic connector is interposed between the support plate and the base. The upper piece includes a cap and outer flanges. The cap overlays the support plate when the upper piece is disposed on the bottom piece. The outer flanges are disposed at edges of the cap, connected with the cap. The outer flanges contact the base of the bottom piece when the upper piece is disposed on the bottom piece. The cap includes an opening which is a through hole. When the upper piece is disposed on the bottom piece, a vertical projection of the opening falls entirely on the support plate.Type: GrantFiled: January 15, 2021Date of Patent: October 31, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Chih-Chien Pan, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
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Patent number: 11799060Abstract: A light-emitting device includes a substrate including a top surface, a first side surface and a second side surface, wherein the first side surface and the second side surface of the substrate are respectively connected to two opposite sides of the top surface of the substrate; a semiconductor stack formed on the top surface of the substrate, the semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first electrode pad formed adjacent to a first edge of the light-emitting device; and a second electrode pad formed adjacent to a second edge of the light-emitting device, wherein in a top view of the light-emitting device, the first edge and the second edge are formed on different sides or opposite sides of the light-emitting device, the first semiconductor layer adjacent to the first edge includes a first sidewall directly connected to the first side surface of the substrate,Type: GrantFiled: February 23, 2023Date of Patent: October 24, 2023Assignee: EPISTAR CORPORATIONInventors: Chao-Hsing Chen, Cheng-Lin Lu, Chih-Hao Chen, Chi-Shiang Hsu, I-Lun Ma, Meng-Hsiang Hong, Hsin-Ying Wang, Kuo-Ching Hung, Yi-Hung Lin
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Publication number: 20230335596Abstract: A semiconductor device includes a semiconductor stack, an insulating structure, an electrode structure, and a protective layer. The insulating structure is disposed on the semiconductor stack and includes a first portion. The first portion includes a first opening exposing an inner sidewall of the insulating structure. The electrode structure includes a metal material. The protective layer is disposed between the inner sidewall and the electrode structure, and includes a second opening. The electrode structure is disposed in the first opening and in contact with the protective layer, and the electrode structure is electrically connected to the semiconductor stack through the second opening. The insulating structure includes a first material, and the protective layer includes a second material.Type: ApplicationFiled: April 19, 2023Publication date: October 19, 2023Applicant: GaNrich Semiconductor CorporationInventors: Chih-Hao Chen, Yi-Ru Shen
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Publication number: 20230326981Abstract: A semiconductor device includes a substrate, a semiconductor stack, an insulating structure, and an electrode. The semiconductor stack is disposed on the substrate and includes a two-dimensional electron gas region. The insulating structure is disposed on the semiconductor stack and includes a first insulating layer and a second insulating layer. The first insulating layer includes a first opening exposing the first inner sidewall of the first insulating layer. The second insulating layer is disposed on the first insulating layer and covers the first inner sidewall of the first insulating layer. The second insulating layer includes a second opening disposed in the first opening and exposing the second inner sidewall of the second insulating layer. The second insulating layer includes a step profile, and a step edge of the step profile coincides with the second inner sidewall. The electrode is disposed on the insulating structure and in the second opening.Type: ApplicationFiled: April 10, 2023Publication date: October 12, 2023Applicant: GaNrich Semiconductor CorporationInventors: Chih-Hao Chen, Yi-Ru Shen
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Publication number: 20230317898Abstract: A light-emitting device comprises a substrate comprising a sidewall, a first top surface, and a second top surface, wherein the second top surface is closer to the sidewall of the substrate than the first top surface to the sidewall of the substrate; a semiconductor stack formed on the substrate comprising a first semiconductor layer, an active layer, and a second semiconductor layer; a dicing street surrounding the semiconductor stack, and exposing the first top surface and the second top surface of the substrate; a protective layer covering the semiconductor stack; a reflective layer comprising a Distributed Bragg Reflector structure covering the protective layer; and a cap layer covering the reflective layer, wherein the second top surface of the substrate is not covered by the protective layer, the reflective layer, and the cap layer.Type: ApplicationFiled: June 5, 2023Publication date: October 5, 2023Applicant: EPISTAR CORPORATIONInventors: Hsin-Ying WANG, Chih-Hao CHEN, Chien-Chih LIAO, Chao-Hsing CHEN, Wu-Tsung LO, Tsun-Kai KO, Chen OU
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Publication number: 20230317552Abstract: A method of forming a semiconductor structure includes: attaching a semiconductor device to a first surface of a substrate; placing a thermal interface material (TIM) film over a first side of the semiconductor device distal from the substrate, where the TIM film is pre-formed before the placing, where after the placing, a peripheral portion of the TIM film extends laterally beyond sidewalls of the semiconductor device; and attaching a lid to the first surface of the substrate to form an enclosed space between the lid and the substrate, where after attaching the lid, the semiconductor device and the TIM film are disposed in the enclosed space, where a first side of the TIM film distal from the substrate contacts the lid.Type: ApplicationFiled: June 2, 2023Publication date: October 5, 2023Inventors: Chih-Hao Chen, Hung-Yu Chen, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
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Publication number: 20230290704Abstract: A package structure includes first and second package components, an underfill layer disposed between the first and second package components, and a metallic layer. The first package component includes semiconductor dies, a first insulating encapsulation laterally encapsulating the semiconductor dies, and a redistribution structure underlying first surfaces of the semiconductor dies and the first insulating encapsulation. The second package component underlying the first package component is electrically coupled to the semiconductor dies through the redistribution structure. The underfill layer extends to cover a sidewall of the first package component, the metallic layer overlying second surfaces of the semiconductor dies and the first insulating encapsulation, and a peripheral region of the second surface of the first insulating encapsulation is accessibly exposed by the metallic layer, where the first surfaces are opposite to the second surfaces.Type: ApplicationFiled: March 14, 2022Publication date: September 14, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Po-Yuan Cheng, Pu Wang, Li-Hui Cheng
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Publication number: 20230290650Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.Type: ApplicationFiled: May 22, 2023Publication date: September 14, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Hui Cheng, Szu-Wei Lu, Ping-Yin Hsieh, Chih-Hao Chen
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Patent number: 11757077Abstract: A light-emitting device comprises a substrate comprising a top surface and a sidewall; a semiconductor stack formed on the top surface of the substrate comprising a first semiconductor layer, an active layer and a second semiconductor layer; a dicing street surrounding the semiconductor stack and exposing the top surface of the substrate; a protective layer covering the semiconductor stack and the dicing street; a reflective layer comprising a Distributed Bragg Reflector structure and covering the protective layer; and a cap layer covering the reflective layer, wherein the reflective layer comprises an uneven portion adjacent to the sidewall of the substrate, and the uneven portion comprises an uneven thickness.Type: GrantFiled: May 3, 2021Date of Patent: September 12, 2023Assignee: EPISTAR CORPORATIONInventors: Hsin-Ying Wang, Chih-Hao Chen, Chien-Chih Liao, Chao-Hsing Chen, Wu-Tsung Lo, Tsun-Kai Ko, Chen Ou
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Patent number: 11756855Abstract: A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer.Type: GrantFiled: January 28, 2022Date of Patent: September 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
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Patent number: 11732193Abstract: A display panel includes a first substrate, an electrode layer, and a display medium layer. The electrode layer is disposed on the first substrate. The display medium layer is disposed on the electrode layer and includes a filler and liquid crystal capsules. The liquid crystal capsules are distributed in the filler, and the filler has a birefringence difference ?n in a range from 0.02 to 0.175.Type: GrantFiled: July 6, 2021Date of Patent: August 22, 2023Assignee: AU OPTRONICS CORPORATIONInventors: Liang-Yin Huang, Chih-Hao Chen, Min-Zi Hong, Seok-Lyul Lee
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Publication number: 20230253321Abstract: A method includes forming a first etch stop layer (ESL) over a conductive feature, forming a first dielectric layer on the first ESL, forming a second ESL on the first dielectric layer, forming a second dielectric layer on the second ESL, forming a trench in the second dielectric layer, forming a first opening in a bottom surface of the trench extending through the second dielectric layer, and forming a second opening in a bottom surface of the first opening. The second opening extends through the first dielectric layer and the first ESL. The second opening exposes a top surface of the conductive feature. The method further includes widening the first opening to a second width, filling the trench with a conductive material to form a conductive line, and filling the second opening and the first opening with the conductive material to form a conductive via.Type: ApplicationFiled: April 18, 2023Publication date: August 10, 2023Inventors: Yen-Chih Huang, Li-An Sun, Che-En Tsai, Yu-Lin Chiang, Chung Chuan Huang, Chih-Hao Chen
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Publication number: 20230253276Abstract: A method for forming a package structure is provided. The method includes bonding a package component to a substrate through a plurality of first connectors. The package component comprises a first semiconductor die and a second semiconductor die. The method also includes forming a dam structure over the substrate and surrounding the first connectors. A top surface of the dam structure is lower than a bottom surface of the package component. The method further includes filling an underfill layer in a space between the dam structure and the first connectors. In addition, the method includes removing the dam structure after the underfill layer is formed.Type: ApplicationFiled: April 18, 2023Publication date: August 10, 2023Inventors: Chih-Hao CHEN, Chih-Chien PAN, Li-Hui CHENG, Chin-Fu KAO, Szu-Wei LU
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Publication number: 20230230898Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.Type: ApplicationFiled: March 10, 2023Publication date: July 20, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu, Chih-Chien Pan