Patents by Inventor Chih-Hao Yu

Chih-Hao Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200321288
    Abstract: A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Inventors: Shih-Ya Huang, Chung-Hao Tsai, Chuei-Tang Wang, Chen-Hua Yu, Chih-Yuan Chang
  • Publication number: 20200303194
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a substrate, a fin structure formed over the substrate, and an isolation structure formed over the substrate. The fin structure protrudes from the isolation structure. The FinFET device structure further includes a fin isolation structure formed over the isolation structure and a metal gate structure formed over the fin structure and the fin isolation structure.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jia-Ni YU, Zhi-Chang LIN, Wei-Hao WU, Huan-Chieh SU, Chung-Wei HSU, Chih-Hao WANG
  • Publication number: 20200294863
    Abstract: A method of fabricating semiconductor devices includes forming a plurality of first and second nanosheets in p-type and n-type device regions, respectively. A p-type work function (PWF) layer is deposited to surround each of the first and second nanosheets. A first mask is formed on the PWF layer and not over the boundary between the p-type and n-type device regions, and then the PWF layer is etched in a first etching process to keep portions of the PWF layer between the second nanosheets. A second mask is formed on the PWF layer, and then the portions of the PWF layer between the second nanosheets are removed in a second etching process. An n-type work function layer is deposited in the n-type and the p-type device regions to surround each of the second nanosheets and on the PWF layer.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 17, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng CHIANG, Chung-Wei HSU, Lung-Kun CHU, Jia-Ni YU, Chih-Hao WANG, Mao-Lin HUANG
  • Patent number: 10777467
    Abstract: A semiconductor structure includes a substrate including a first surface and a second surface opposite to the first surface; a dielectric layer disposed over the second surface or below the first surface; a polymeric layer disposed over or below the dielectric layer; an isolation layer surrounding and contacted with the substrate, the dielectric layer and the polymeric layer; a die disposed over the polymeric layer; a first conductive bump disposed below the first surface of the substrate; and a second conductive bump disposed between the second surface of the substrate and the die.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Yang Yu, Chien-Kuo Chang, Chih-Hao Lin, Jung Tsung Cheng, Kuan-Lin Ho
  • Patent number: 10763164
    Abstract: A package structure includes a first redistribution layer, a molding material, a semiconductor device and an inductor. The molding material is located on the first redistribution layer. The semiconductor device is molded in the molding material. The inductor penetrates through the molding material and electrically connected to the semiconductor device.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Lin Chen, Chung-Hao Tsai, Jeng-Shien Hsieh, Chuei-Tang Wang, Chen-Hua Yu, Chih-Yuan Chang
  • Publication number: 20200264503
    Abstract: The present disclosure provides an embodiment of a reflective mask that includes a substrate; a reflective multilayer disposed on the substrate; an anti-oxidation barrier layer disposed on the reflective multilayer and the anti-oxidation barrier layer is in amorphous structure with an average interatomic distance less than an oxygen diameter; and an absorber layer disposed on the anti-oxidation barrier layer and patterned according to an integrated circuit layout.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Inventors: Chia-Hao Yu, Chi-Lun Lu, Chih-Tsung Shih, Ching-Wei Shen, Jeng-Horng Chen
  • Publication number: 20200243519
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first epitaxial structure and a second epitaxial structure over a semiconductor substrate. The method includes forming a dielectric layer over the first epitaxial structure, the second epitaxial structure, and the semiconductor substrate. The method includes forming a first mask layer over the dielectric layer and between the first epitaxial structure and the second epitaxial structure. The method includes forming a second mask layer over the dielectric layer and the first mask layer. The method includes partially removing the dielectric layer covering the first epitaxial structure and the second epitaxial structure. The method includes removing the first mask layer. The method includes forming a first conductive layer and a second conductive layer respectively in the first recess and the second recess.
    Type: Application
    Filed: January 25, 2019
    Publication date: July 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Zhen YU, Tien-Lu LIN, Jia-Chuan YOU, Chia-Hao CHANG, Yu-Ming LIN, Chih-Hao WANG
  • Patent number: 10727064
    Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a first deposition process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes performing an etch process to remove a portion of the conformal film. The method includes repeating the first deposition process and the etch process to fill the feature with the conformal film. The method includes exposing the conformal film to ultraviolet light.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: De-Wei Yu, Chien-Hao Chen, Chih-Tang Peng, Jei Ming Chen, Shu-Yi Wang
  • Publication number: 20200212217
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Application
    Filed: December 24, 2019
    Publication date: July 2, 2020
    Inventors: Shao-Ming YU, Chang-Yun CHANG, Chih-Hao CHANG, Hsin-Chih CHEN, Kai-Tai CHANG, Ming-Feng SHIEH, Kuei-Liang LU, Yi-Tang LIN
  • Publication number: 20200203280
    Abstract: A semiconductor package structure and manufacturing method thereof are provided. The semiconductor package structure includes a package structure and a rigid-flexible substrate. The package structure includes semiconductor dies, a molding compound and a redistribution layer. The molding compound laterally encapsulates the semiconductor dies. The redistribution layer is disposed at a front side of the semiconductor dies and electrically connected to the semiconductor dies. The rigid-flexible substrate is disposed at a side of the redistribution layer opposite to the semiconductor dies, and includes rigid structures, a flexible core and a circuit layer. The rigid structures respectively have an interconnection structure therein. The interconnection structures are electrically connected to the redistribution layer. The flexible core laterally penetrates and connects the rigid structures.
    Type: Application
    Filed: December 24, 2018
    Publication date: June 25, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chuei-Tang Wang, Chen-Hua Yu, Chung-Shi Liu, Chih-Yuan Chang, Jiun-Yi Wu, Jeng-Shien Hsieh, Tin-Hao Kuo
  • Patent number: 10692817
    Abstract: A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ya Huang, Chung-Hao Tsai, Chuei-Tang Wang, Chen-Hua Yu, Chih-Yuan Chang
  • Publication number: 20200192021
    Abstract: A light guide assembly includes a light guide plate and a light source. The light guide plate has a through hole, an inner sidewall that surrounds the through hole, and an outer sidewall that surrounds the inner sidewall. The inner sidewall has a halo elimination structure that faces the through hole. The outer sidewall has a light incident surface. The light source faces the light incident surface of the outer sidewall of the light guide plate.
    Type: Application
    Filed: November 6, 2019
    Publication date: June 18, 2020
    Inventors: Hsin-Hao JEN, Tsai-Wei SHEI, Chin-Chi YU, Chih-Chun CHEN
  • Patent number: 10679856
    Abstract: A method for forming a FinFET device structure is provided. The method for forming a FinFET device structure includes forming a fin structure and a fin isolation structure over a substrate, and forming a metal stack over the fin structure and the fin isolation structure. The method for forming a FinFET device structure also includes partially removing the metal stack so that a top surface of the fin isolation structure is exposed, and forming a dielectric material over the metal stack and covering the top surface of the fin isolation structure. The method for forming a FinFET device structure further includes patterning the dielectric material and the metal stack to form a metal gate structure and an insulating structure over the metal gate structure.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Ni Yu, Zhi-Chang Lin, Wei-Hao Wu, Huan-Chieh Su, Chung-Wei Hsu, Chih-Hao Wang
  • Publication number: 20200174187
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a photonic die, an encapsulant and a wave guide structure. The photonic die includes a substrate and a dielectric layer. The substrate has a wave guide pattern. The dielectric layer is disposed over the substrate. The photonic die is encapsulated by the encapsulant. The wave guide structure spans over the front side of the photonic die and a top surface of the encapsulant, and penetrates the dielectric layer to be optically coupled with the wave guide pattern.
    Type: Application
    Filed: September 13, 2019
    Publication date: June 4, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chieh Chang, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang
  • Patent number: 10670257
    Abstract: A waterproof light emitting module includes a circuit board, a light emitting diode, a light guide plate, first, second, and third waterproof layers. The light emitting diode is over the circuit board and has a light emitting surface, and first and second non-light emitting surfaces. The light emitting surface is opposite to the first non-light emitting surface. The second non-light emitting surface is between the light emitting surface and the first non-light emitting surface. A center of the light guide plate is substantially aligned with a center of the light emitting diode along a direction perpendicular to the light emitting surface. The light emitting diode is between the first waterproof layer and the light guide plate. The second waterproof layer covers the second non-light emitting surface. The third waterproof layer is between the second waterproof layer and the light guide plate.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: June 2, 2020
    Assignee: E Ink Holdings Inc.
    Inventors: Tsai-Wei Shei, Chih-Ching Yen, Hsin-Hao Jen, Chin-Chi Yu, Chih-Chun Chen
  • Patent number: 10642148
    Abstract: The present disclosure provides an embodiment of a reflective mask that includes a substrate; a reflective multilayer disposed on the substrate; an anti-oxidation barrier layer disposed on the reflective multilayer and the anti-oxidation barrier layer is in amorphous structure with an average interatomic distance less than an oxygen diameter; and an absorber layer disposed on the anti-oxidation barrier layer and patterned according to an integrated circuit layout.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: May 5, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hao Yu, Chi-Lun Lu, Chih-Tsung Shih, Ching-Wei Shen, Jeng-Horng Chen
  • Publication number: 20200127105
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a fin structure on a substrate; forming a dummy gate over the fin structure; forming spacers on sides of the dummy gate; forming a doped region within the fin structure; replacing the dummy gate with a metal gate; replacing an upper portion of the metal gate with a first dielectric layer; forming a conductive layer directly on the doped region; replacing an upper portion of the conductive layer with a second dielectric layer; removing the first dielectric layer thereby exposing a sidewall of the spacer; removing an upper portion of the spacer to thereby expose a sidewall of the second dielectric layer; removing at least a portion of the second dielectric layer to form a trench; and forming a conductive plug in the trench.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 23, 2020
    Inventors: Wei-Hao Wu, Chia-Hao Chang, Chih-Hao Wang, Jia-Chuan You, Yi-Hsiung Lin, Zhi-Chang Lin, Chia-Hao Kuo, Ke-Jing Yu
  • Publication number: 20200127117
    Abstract: A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. A width of the separation plug in a second direction perpendicular to the first direction is smaller than a width of the first gate structure in the second direction, when viewed in plan view.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Inventors: Chih-Hao YU, Sheng-Chen WANG, Sai-Hooi YEONG
  • Publication number: 20200105937
    Abstract: A method includes providing a semiconductor structure having metal gate structures (MGs), gate spacers disposed on sidewalls of the MGs, and source/drain (S/D) features disposed adjacent to the gate spacers; forming a first dielectric layer over the MGs and forming S/D contacts (MDs) over the S/D features; forming a second dielectric layer over the first dielectric layer, where portions of the second dielectric layer contact the MDs and the second dielectric layer is different from the first dielectric layer in composition; removing the portions of the second dielectric layer that contact the MDs; forming a conductive layer over the MDs and over the first dielectric layer; and removing portions of the conductive layer to form conductive features over the MDs.
    Type: Application
    Filed: July 17, 2019
    Publication date: April 2, 2020
    Inventors: Li-Zhen Yu, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20200098622
    Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.
    Type: Application
    Filed: July 12, 2019
    Publication date: March 26, 2020
    Inventors: Huan-Chieh Su, Chih-Hao Wang, Kuo-Cheng Chiang, Wei-Hao Wu, Zhi-Chang Lin, Jia-Ni Yu, Yu-Ming Lin, Chung-Wei Hsu