Patents by Inventor Chih-Hao Yu

Chih-Hao Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7804141
    Abstract: A semiconductor element structure includes a first MOS having a first high-K material and a first metal for use in a first gate, a second MOS having a second high-K material and a second metal for use in a second gate and a bridge channel disposed in a recess connecting the first gate and the second gate for electrically connecting the first gate and the second gate, wherein the bridge channel is embedded in at least one of the first gate and the second gate.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: September 28, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Tian-Fu Chiang, Li-Wei Cheng, Che-Hua Hsu, Chih-Hao Yu, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma
  • Patent number: 7799630
    Abstract: A method for manufacturing a CMOS device having dual metal gate includes providing a substrate having at least two transistors of different conductive types and a dielectric layer covering the two transistors, planarizing the dielectric layer to expose gate conductive layers of the two transistors, forming a patterned blocking layer exposing one of the conductive type transistor, performing a first etching process to remove a portion of a gate of the conductive type transistor, reforming a metal gate, removing the patterned blocking layer, performing a second etching process to remove a portion of a gate of the other conductive type transistor, and reforming a metal gate.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: September 21, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Hao Yu, Li-Wei Cheng, Tian-Fu Chiang, Cheng-Hsien Chou, Chien-Ting Lin, Che-Hua Hsu, Guang-Hwa Ma
  • Publication number: 20100059833
    Abstract: A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.
    Type: Application
    Filed: September 11, 2008
    Publication date: March 11, 2010
    Inventors: Chih-Hao Yu, Li-Wei Cheng, Che-Hua Hsu, Cheng-Hsien Chou, Tian-Fu Chiang, Chien-Ming Lai, Yi-Wen Chen, Jung-Tsung Tseng, Chien-Ting Lin, Guang-Hwa Ma
  • Publication number: 20100052074
    Abstract: A method for fabricating a transistor having metal gate is disclosed. First, a substrate is provided, in which the substrate includes a first transistor region and a second transistor region. A plurality of dummy gates is formed on the substrate, and a dielectric layer is deposited on the dummy gate. The dummy gates are removed to form a plurality of openings in the dielectric layer. A high-k dielectric layer is formed to cover the surface of the dielectric layer and the opening, and a cap layer is formed on the high-k dielectric layer thereafter. The cap layer disposed in the second transistor region is removed, and a metal layer is deposited on the cap layer of the first transistor region and the high-k dielectric layer of the second transistor region. A conductive layer is formed to fill the openings of the first transistor region and the second transistor region.
    Type: Application
    Filed: August 26, 2008
    Publication date: March 4, 2010
    Inventors: Chien-Ting Lin, Li-Wei Cheng, Jung-Tsung Tseng, Che-Hua Hsu, Chih-Hao Yu, Tian-Fu Chiang, Yi-Wen Chen, Chien-Ming Lai, Cheng-Hsien Chou
  • Publication number: 20100002453
    Abstract: An illuminating device and an annular heat-dissipating structure thereof. The annular heat-dissipating structure includes a plurality of heat-dissipating units disposed circumambiently. Each heat-dissipating unit includes a flake and at least one first assembling portion connected with the flake, so that the adjacent heat-dissipating units can be connected with each other.
    Type: Application
    Filed: October 28, 2008
    Publication date: January 7, 2010
    Inventors: Hsiang-Chen WU, Chin-Ming Cheng, Chih-Hao Yu, Te-Hsin Chiu, Han-Chung Hsu
  • Patent number: 7611213
    Abstract: Sliding track assembly is provided. A sliding track assembly includes a first rail, a second rail reciprocally moved with respect to the first rail, a third rail reciprocally moved with respect to the second rail, and a latch mechanism disposed on the second rail. The first rail has a retaining block, and the third rail has a protrusion. The latch mechanism includes a pair of swing arms engaged against the retaining block. When the latch mechanism is forced by the protrusion, the pair of swing arms is swung outwardly and disengaged from the retaining block.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: November 3, 2009
    Assignee: Atom International Co., Ltd.
    Inventors: Sui-An Wu, Chih-Hao Yu
  • Publication number: 20090242997
    Abstract: A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 1, 2009
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Hao Yu, Li-Wei Cheng, Che-Hua Hsu, Tian-Fu Chiang, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma
  • Publication number: 20090236669
    Abstract: A method for fabricating metal gate transistors and a polysilicon resistor is disclosed. First, a substrate having a transistor region and a resistor region is provided. A polysilicon layer is then formed on the substrate to cover the transistor region and the resistor region of the substrate. Next, a portion of the polysilicon layer disposed in the resistor is removed, and the remaining polysilicon layer is patterned to create a step height between the surface of the polysilicon layer disposed in the transistor region and the surface of the polysilicon layer disposed in the resistor region.
    Type: Application
    Filed: March 20, 2008
    Publication date: September 24, 2009
    Inventors: Yi-Wen Chen, Li-Wei Cheng, Che-Hua Hsu, Chih-Hao Yu, Cheng-Hsien Chou, Chien-Ming Lai, Tian-Fu Chiang, Chien-Ting Lin, Guang-Hwa Ma
  • Publication number: 20090206415
    Abstract: A semiconductor element structure includes a first MOS having a first high-K material and a first metal for use in a first gate, a second MOS having a second high-K material and a second metal for use in a second gate and a bridge channel disposed in a recess connecting the first gate and the second gate for electrically connecting the first gate and the second gate, wherein the bridge channel is embedded in at least one of the first gate and the second gate.
    Type: Application
    Filed: February 19, 2008
    Publication date: August 20, 2009
    Inventors: Tian-Fu Chiang, Li-Wei Cheng, Che-Hua Hsu, Chih-Hao Yu, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma
  • Publication number: 20090186458
    Abstract: A method for manufacturing a CMOS device having dual metal gate includes providing a substrate having at least two transistors of different conductive types and a dielectric layer covering the two transistors, planarizing the dielectric layer to expose gate conductive layers of the two transistors, forming a patterned blocking layer exposing one of the conductive type transistor, performing a first etching process to remove a portion of a gate of the conductive type transistor, reforming a metal gate, removing the patterned blocking layer, performing a second etching process to remove a portion of a gate of the other conductive type transistor, and reforming a metal gate.
    Type: Application
    Filed: January 23, 2008
    Publication date: July 23, 2009
    Inventors: Chih-Hao Yu, Li-Wei Cheng, Tian-Fu Chiang, Cheng-Hsien Chou, Chien-Ting Lin, Che-Hua Hsu, Guang-Hwa Ma
  • Publication number: 20080297700
    Abstract: A light-emitting module includes a plurality of lamp units and a plurality of LED units. The lamp unit generates first non-white colored light. The LED unit generates second colored light. Each LED unit is disposed between the lamp units. The first non-white colored light and the second colored light are mixed to generate third colored light. A backlight module and a liquid crystal display (LCD) are also disclosed.
    Type: Application
    Filed: August 9, 2007
    Publication date: December 4, 2008
    Inventors: Chih-Hao Yu, Nai-Yueh Liang
  • Publication number: 20080224585
    Abstract: Sliding track assembly is provided. A sliding track assembly includes a first rail, a second rail reciprocally moved with respect to the first rail, a third rail reciprocally moved with respect to the second rail, and a latch mechanism disposed on the second rail. The first rail has a retaining block, and the third rail has a protrusion. The latch mechanism includes a pair of swing arms engaged against the retaining block. When the latch mechanism is forced by the protrusion, the pair of swing arms is swung outwardly and disengaged from the retaining block.
    Type: Application
    Filed: March 13, 2007
    Publication date: September 18, 2008
    Applicant: ATEN INTERNATIONAL CO., LTD.
    Inventors: Sui-An Wu, Chih-Hao Yu
  • Publication number: 20080025023
    Abstract: A light-emitting heat-dissipating device includes a substrate and at least a light-emitting package module capable of generating heat. The substrate includes at least a recess and at least one thermally conducting element disposed in the recess. The light-emitting package module is disposed on the thermally conducting element and electrically connected to the substrate of the substrate via solder joints. A manufacturing method of the light-emitting heat-dissipating device is also disclosed.
    Type: Application
    Filed: July 23, 2007
    Publication date: January 31, 2008
    Inventors: Yu-Ping Hsieh, Yi-Sheng Lee, Chin-Ming Cheng, Chih-Hao Yu, Yu-Ching Chang, Yi-Hong Huang
  • Publication number: 20080023722
    Abstract: A light-emitting heat-dissipating device includes at least one light-emitting chip and a circuit board. The circuit board has at least one recess and at least one thermally conducting element disposed in the recess. The light-emitting chip is disposed on the thermally conducting element and connected to the circuit board via contact pads electrically connected to a circuit layout of the circuit board. In addition, the light-emitting chip is package by a filler on the circuit board. A packaging method of the light-emitting heat-dissipating device is also disclosed.
    Type: Application
    Filed: July 23, 2007
    Publication date: January 31, 2008
    Inventors: Yi-Sheng Lee, Chih-Hao Yu, Chin-Ming Cheng, Yu-Ping Hsieh, Yu-Ching Chang, Yi-Hong Huang