Patents by Inventor Chih-Hao Yu
Chih-Hao Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180240891Abstract: A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. A width of the separation plug in a second direction perpendicular to the first direction is smaller than a width of the first gate structure in the second direction, when viewed in plan view.Type: ApplicationFiled: April 23, 2018Publication date: August 23, 2018Inventors: Chih-Hao YU, Sheng-chen WANG, Sai-Hooi YEONG
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Patent number: 10030158Abstract: The invention relates to an ink composition suitable for applications onto solar cells. Specifically, the invention describes several compositions, using nickel/silicon alloys which have been found to be particularly effective contact metallization of emitter layers. The ratio of nickel to silicon in claimed invention is in the range of 0.1:1 to 1:0.1.Type: GrantFiled: November 6, 2013Date of Patent: July 24, 2018Assignee: Intrinsiq Materials Ltd.Inventors: Richard Dixon, Jose Pedrosa, Kai Man Kerry Yu, Chih-Hao Yu
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Patent number: 9954076Abstract: A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. A width of the separation plug in a second direction perpendicular to the first direction is smaller than a width of the first gate structure in the second direction, when viewed in plan view.Type: GrantFiled: April 13, 2017Date of Patent: April 24, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hao Yu, Sheng-chen Wang, Sai-Hooi Yeong
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Publication number: 20170222020Abstract: A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. A width of the separation plug in a second direction perpendicular to the first direction is smaller than a width of the first gate structure in the second direction, when viewed in plan view.Type: ApplicationFiled: April 13, 2017Publication date: August 3, 2017Inventors: Chih-Hao YU, Sheng-chen WANG, Sai-Hooi YEONG
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Patent number: 9659930Abstract: A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. A width of the separation plug in a second direction perpendicular to the first direction is smaller than a width of the first gate structure in the second direction, when viewed in plan view.Type: GrantFiled: November 4, 2015Date of Patent: May 23, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hao Yu, Sheng-chen Wang, Sai-Hooi Yeong
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Publication number: 20170125411Abstract: A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. A width of the separation plug in a second direction perpendicular to the first direction is smaller than a width of the first gate structure in the second direction, when viewed in plan view.Type: ApplicationFiled: November 4, 2015Publication date: May 4, 2017Inventors: Chih-Hao YU, Sheng-chen WANG, Sai-Hooi YEONG
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Publication number: 20160343710Abstract: A semiconductor device includes a first fin structure extending from a semiconductor substrate. A second fin structure is disposed over the first fin structure. The second fin structure includes a first layer including a first semiconductor material. The second fin structure further includes a second layer including a second semiconductor material disposed over the first layer. The second layer has a vertical sidewall. The second semiconductor material is different from the first semiconductor material. A gate structure is disposed over the semiconductor substrate and wraps around the first and second layers of the second fin structure.Type: ApplicationFiled: August 1, 2016Publication date: November 24, 2016Inventors: Chih-Hao YU, Shao-Ming YU
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Patent number: 9406782Abstract: A method for fabricating a fin-type field-effect transistor (FinFET) device includes forming a first fin structure over a substrate, forming a dielectric layer over the first fin structures, forming a trench with a vertical profile in the dielectric layer, depositing conformably a first semiconductor material layer over sidewalls and bottom of the trench, depositing a second semiconductor material layer over the first semiconductor material layer to filling in the remaining trench, recessing the dielectric layer to laterally expose the first semiconductor material layer and etching the exposed first semiconductor material layer to reveal the second semiconductor material layer.Type: GrantFiled: June 27, 2014Date of Patent: August 2, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Yu, Shao-Ming Yu
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Publication number: 20150380525Abstract: A method for fabricating a fin-type field-effect transistor (FinFET) device includes forming a first fin structure over a substrate, forming a dielectric layer over the first fin structures, forming a trench with a vertical profile in the dielectric layer, depositing conformably a first semiconductor material layer over sidewalls and bottom of the trench, depositing a second semiconductor material layer over the first semiconductor material layer to filling in the remaining trench, recessing the dielectric layer to laterally expose the first semiconductor material layer and etching the exposed first semiconductor material layer to reveal the second semiconductor material layer.Type: ApplicationFiled: June 27, 2014Publication date: December 31, 2015Inventors: Chih-Hao Yu, Shao-Ming Yu
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Patent number: 9214558Abstract: A method includes forming a gate structure on a semiconductor material region, wherein the gate structure includes spacer elements abutting a gate electrode layer. The gate electrode layer is etched to provide a recess. A hard mask layer is formed over the gate electrode layer in the recess. Silicide layers are then formed on a source region and a drain region disposed in the semiconductor material region, while the hard mask is disposed over the gate electrode layer. A source contact and a drain contact is then provided, each source and drain contact being conductively coupled to a respective one of the silicide layers.Type: GrantFiled: February 27, 2014Date of Patent: December 15, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Ming Chen, Chih-Hao Chang, Chih-Hao Yu
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Patent number: 8860150Abstract: The metal gate structure of the present invention can include a TiN complex, and the N/Ti proportion of the TiN complex is decreased from bottom to top. In one embodiment, the TiN complex can include a single TiN layer, which has an N/Ti proportion gradually decreasing from bottom to top. In another embodiment, the TiN complex can include a plurality of TiN layers stacking together. In such a case, the lowest TiN layer has a higher N/Ti proportion than the adjusted TiN layer.Type: GrantFiled: December 10, 2009Date of Patent: October 14, 2014Assignee: United Microelectronics Corp.Inventors: Chin-Fu Lin, Nien-Ting Ho, Chun-Hsien Lin, Chih-Hao Yu, Cheng-Hsien Chou
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Patent number: 8847295Abstract: A structure and method of forming a semiconductor device with a fin is provided. In an embodiment a hard mask is utilized to pattern a gate electrode layer and is then removed. After the hard mask has been removed, the gate electrode layer may be separated into individual gate electrodes.Type: GrantFiled: August 1, 2013Date of Patent: September 30, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Feng Shieh, Chih-Hao Yu, Chang-Yun Chang
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Patent number: 8816439Abstract: A gate structure of a semiconductor device includes a first low resistance conductive layer, a second low resistance conductive layer, and a first type conductive layer disposed between and directly contacting sidewalls of the first low resistance conductive layer and the second low resistance conductive layer.Type: GrantFiled: October 19, 2010Date of Patent: August 26, 2014Assignee: United Microelectronics Corp.Inventors: Chih-Hao Yu, Li-Wei Cheng, Che-Hua Hsu, Tian-Fu Chiang, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma
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Publication number: 20140179077Abstract: A method includes forming a gate structure on a semiconductor material region, wherein the gate structure includes spacer elements abutting a gate electrode layer. The gate electrode layer is etched to provide a recess. A hard mask layer is formed over the gate electrode layer in the recess. Silicide layers are then formed on a source region and a drain region disposed in the semiconductor material region, while the hard mask is disposed over the gate electrode layer. A source contact and a drain contact is then provided, each source and drain contact being conductively coupled to a respective one of the silicide layers.Type: ApplicationFiled: February 27, 2014Publication date: June 26, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Ming Chen, Chih-Hao Chang, Chih-Hao Yu
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Patent number: 8686516Abstract: Improved silicide formation and associated devices are disclosed. An exemplary semiconductor device includes a semiconductor substrate, a fin structure disposed over the semiconductor substrate and having spaced source and drain regions extending outwardly from a channel region, and a gate structure disposed on a portion of the fin structure, the gate structure engaging the fin structure adjacent to the channel region. The device also includes a first silicide layer disposed on the fin structure, the first silicide layer extending outwardly from the gate structure along a top portion of the source region and a second silicide layer disposed on the fin structure, the second silicide layer extending outwardly from the gate structure along a top portion of the drain region. Further, the device includes a source contact conductively coupled to the first silicide layer and a drain contact conductively coupled to the second silicide layer.Type: GrantFiled: June 17, 2013Date of Patent: April 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Ming Chen, Chih-Hao Chang, Chih-Hao Yu
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Patent number: 8623721Abstract: Improved silicide formation and associated devices are disclosed. An exemplary method includes providing a semiconductor material having spaced source and drain regions therein, forming a gate structure interposed between the source and drain regions, performing a gate replacement process on the gate structure to form a metal gate electrode therein, forming a hard mask layer over the metal gate electrode, forming silicide layers on the respective source and drain regions in the semiconductor material, removing the hard mask layer to expose the metal gate electrode, and forming source and drain contacts, each source and drain contact being conductively coupled to a respective one of the silicide layers.Type: GrantFiled: June 17, 2013Date of Patent: January 7, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Ming Chen, Chih-Hao Chang, Chih-Hao Yu
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Publication number: 20140001574Abstract: Improved silicide formation and associated devices are disclosed. An exemplary semiconductor device includes a semiconductor substrate, a fin structure disposed over the semiconductor substrate and having spaced source and drain regions extending outwardly from a channel region, and a gate structure disposed on a portion of the fin structure, the gate structure engaging the fin structure adjacent to the channel region. The device also includes a first silicide layer disposed on the fin structure, the first silicide layer extending outwardly from the gate structure along a top portion of the source region and a second silicide layer disposed on the fin structure, the second silicide layer extending outwardly from the gate structure along a top portion of the drain region. Further, the device includes a source contact conductively coupled to the first silicide layer and a drain contact conductively coupled to the second silicide layer.Type: ApplicationFiled: June 17, 2013Publication date: January 2, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Ming Chen, Chih-Hao Chang, Chih-Hao Yu
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Publication number: 20130313646Abstract: A structure and method of forming a semiconductor device with a fin is provided. In an embodiment a hard mask is utilized to pattern a gate electrode layer and is then removed. After the hard mask has been removed, the gate electrode layer may be separated into individual gate electrodes.Type: ApplicationFiled: August 1, 2013Publication date: November 28, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Feng Shieh, Chih-Hao Yu, Chang-Yun Chang
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Publication number: 20130280899Abstract: Improved silicide formation and associated devices are disclosed. An exemplary method includes providing a semiconductor material having spaced source and drain regions therein, forming a gate structure interposed between the source and drain regions, performing a gate replacement process on the gate structure to form a metal gate electrode therein, forming a hard mask layer over the metal gate electrode, forming silicide layers on the respective source and drain regions in the semiconductor material, removing the hard mask layer to expose the metal gate electrode, and forming source and drain contacts, each source and drain contact being conductively coupled to a respective one of the silicide layers.Type: ApplicationFiled: June 17, 2013Publication date: October 24, 2013Inventors: Hung-Ming Chen, Chih-Hao Chang, Chih-Hao Yu
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Patent number: 8513078Abstract: A structure and method of forming a semiconductor device with a fin is provided. In an embodiment a hard mask is utilized to pattern a gate electrode layer and is then removed. After the hard mask has been removed, the gate electrode layer may be separated into individual gate electrodes.Type: GrantFiled: December 22, 2011Date of Patent: August 20, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Feng Shieh, Chih-Hao Yu, Chang-Yun Chang