Abstract: A backlight module comprises an outer frame unit, a light guide plate arranged in the outer frame unit, a light-emitting unit, a plurality of adhesives for fixing the light-emitting unit on the light guide plate, and a plurality of abutting structures. The light-emitting unit includes a flexible circuit board and a plurality of light-emitting elements arranged on the flexible circuit board at intervals. Part of the flexible circuit board is deformed at a specific position by the abutting structures, and the position of the light-emitting elements relative to the light guide plate can be adjusted. Thereby, the light-emitting elements can be aligned with the light incident surface of the light guide plate, prevent light from leaking from the light emitting surface of the light guide plate close to the light-emitting elements, and reduce the generation of bright lines and improving the overall uniformity. The present invention also provides a display device including the backlight module.

Abstract: A light-adjusting device having first regions and second regions is provided. The light-adjusting device includes pillars that form several groups of meta structures. The groups of meta structures correspond to the first regions, and from a top view, the first regions and the second regions are arranged in a checkerboard pattern.

Abstract: The disclosure provides a limit device and a robot using the same. The limit device comprises a first connecting member, a transmission rod and a second connecting member. The first connecting member comprising a first main body portion and two first connecting elements. The two first connecting elements are arranged at intervals. The two first connecting elements are respectively connected to the first main body. The transmission rod comprising a first end and a second end. The first end and the second end are arranged at intervals. The first end penetrates through one of the two first connecting elements. The second end penetrates through the other one of the two first connecting element. The second connecting member provided with two indexing buckles. The two indexing buckles are arranged at intervals, each of the indexing buckles comprises a first limiting groove and a second limiting groove.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: A semiconductor device includes first and second active regions extending in parallel in a substrate, a plurality of conductive patterns, each conductive pattern of the plurality of conductive patterns extending on the substrate across each of the first and second active regions, and a plurality of metal lines, each metal line of the plurality of metal lines overlying and extending across each of the first and second active regions. Each conductive pattern of the plurality of conductive patterns is electrically connected in parallel with each metal line of the plurality of metal lines.

Abstract: A method includes forming a first gate spacer and a second gate spacer on a sidewall of a first gate structure. The first gate spacer is between the second gate spacer and the first gate structure. A first interlayer dielectric (ILD) layer is formed to surround the first gate spacer, the second gate spacer, and the first gate structure. A portion of the second gate spacer and a portion of the first ILD layer are removed simultaneously. A top surface of the second gate spacer is lower than a top surface of the first ILD layer.

Abstract: An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.

Abstract: A task dispatching method for EPD tag devices includes receiving a task command; the server system forwarding the task command to a target router to which the target EPD tag device is connected; the target router checking whether the target EPD tag device is currently connected thereto; when it is determined that the target EPD tag device is not currently connected to the target router, the target router notifying the server system that the target EPD tag device is offline; in response to receiving an online notification indicating that the target EPD tag device is connected to another router, the server system updating a connection list accordingly, and forwarding the task command to an updated target router; and when it is determined that the target EPD tag device is currently connected to the target router, the target router delivering the task command to the target EPD tag device.

Abstract: A non-metal spring includes two non-metal elastic units connected to each other and formed between two non-metal terminal rings. Each of the non-metal elastic units includes two intermediate rings intersecting each other, thereby providing two cross portions. The cross portions of each of the non-metal elastic units divide each of the intermediate rings into a first portion and a second portion. The first portions of the intermediate rings of one of the non-metal elastic units are connected to one of the terminal rings. The second portions of the intermediate rings of another one of the non-metal elastic units are connected to a remaining one of the terminal rings. The first portions of the intermediate rings of each of the non-metal elastic units are connected to the second portions of the intermediate rings of an adjacent one of the non-metal elastic units.

Abstract: A voltage-controlled oscillator device includes first and second voltage-controlled oscillators, a first switch group including two first switches, and a second switch group including two second switches. The first voltage-controlled oscillator includes a first inductor group, a first negative resistance circuit and a first voltage output terminal group. The second voltage-controlled oscillator includes a second inductor group, a second negative resistance circuit and a second voltage output terminal group. For the first switch group, first control terminals are electrically connected to the first voltage output terminal group, first input terminals are electrically connected to the second voltage output terminal group, first output terminals are electrically connected.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The top electrode has interior surfaces defining a recess within an upper surface of the top electrode. A masking layer contacts a bottom of the recess and extends to over the upper surface of the top electrode. An interconnect extends through the masking layer and to the top electrode. The interconnect is directly over the upper surface of the top electrode.

Abstract: A memory device includes a bottom electrode, a buffer element, a metal-containing oxide portion, a resistance switch element, and a top electrode. The buffer element is over the bottom electrode. The metal-containing oxide portion is over the buffer element, in which the metal-containing oxide portion has a same metal material as that of the buffer element. The resistance switch element is over the metal-containing oxide portion. The top electrode is over the resistance switch element.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.

Abstract: A resistive memory device includes an ultrathin barrier layer disposed between the bottom electrode and the bottom electric contact to the memory device. The ultrathin barrier layer may reduce the overall step height of the resistive memory elements by 15% or more, including up to about 20% or more. The use of an ultrathin barrier layer may additionally improve the uniformity of the thickness of the dielectric etch stop layer that partially underlies and extends between the memory elements by at least about 15%. The use of an ultrathin barrier layer may result in improved manufacturability and provide reduced costs and higher yields for resistive memory devices, and may facilitate integration of resistive memory devices in advanced technology nodes.

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

Abstract: A method for fabricating a memory device is provided. The method includes forming a bottom electrode layer over a substrate; forming a buffer layer over the bottom electrode layer; performing a surface treatment to a top surface of the buffer layer; depositing a resistance switch layer over the top surface of the buffer layer after performing the surface treatment; forming a top electrode over the resistance switch layer; and patterning the resistance switch layer into a resistance switch element below the top electrode.

Abstract: A voltage-controlled oscillator device includes first and second voltage-controlled oscillators, a first switch group including two first switches, and a second switch group including two second switches. The first voltage-controlled oscillator includes a first inductor group, a first negative resistance circuit and a first voltage output terminal group. The second voltage-controlled oscillator includes a second inductor group, a second negative resistance circuit and a second voltage output terminal group. For the first switch group, first control terminals are electrically connected to the first voltage output terminal group, first input terminals are electrically connected to the second voltage output terminal group, first output terminals are electrically connected.

Abstract: A production schedule estimation method and a production schedule estimation system are provided. The production schedule estimation method includes the following steps. Current-day work-in-process data, machine group cycle time data of a machine group, and productivity data of the machine group are obtained. The current-day work-in-process data, the cycle time data of the machine group, and the productivity data of the machine group are inputted into a prediction model. Current-day cycle time data and a current-day move volume for each of multiple stations in the machine group are calculated through the prediction model. And, current-day move data is calculated according to the current-day cycle time data and the current-day move volume for each of the multiple stations in the machine group.