Abstract: Oscillators and methods for realignment of an oscillator are provided. An oscillator includes an inductor having first and second terminals and a capacitor electrically coupled in parallel to the inductor at the first and second terminals. A first transistor of a first conductivity type is electrically coupled to the first terminal and a voltage source. The first transistor includes a gate configured to receive a first realignment signal. When the first realignment signal is in a realignment state, the first transistor is turned on and a voltage of the first terminal is increased from a low level to a high level in order to align a phase of a waveform of the oscillator.

Abstract: Phase-locked loops (PLLs) are provided. A PLL includes a voltage-controlled oscillator (VCO), a frequency divider, a track-and-hold charge pump, and a frequency tracking circuit. The VCO is configured to provide an output clock corresponding to a pumping current. The frequency divider is configured to divide the output clock to provide a feedback signal. The track-and-hold charge pump is configured to provide the pumping current according to a reference clock and the feedback signal. The frequency tracking circuit is configured to decrease frequency error between the feedback signal and the reference clock. The track-and-hold charge pump includes a pumping switch and a pulse width modulator (PWM). The PWM is configured to provide a PWM signal to control the pumping switch according to the reference clock, so as to provide the pumping current corresponding to the feedback signal.

Abstract: A semiconductor integrated circuit comprises a semiconductor substrate having a via-hole, a front-side-metal layer formed on a top surface of the semiconductor substrate, a seed-metal layer and a backside-metal layer. A bottom surface of an inner surface of the via-hole is at least partially defined by the front-side-metal layer. A surrounding surface of the inner surface of the via-hole is at least partially defined by the semiconductor substrate. The seed-metal layer is formed on the inner surface of the via-hole and a bottom surface of the semiconductor substrate such that the seed-metal layer and the front-side-metal layer are connected. The backside-metal layer is formed on an outer surface of the seed-metal layer. An aspect ratio of the via-hole is greater than or equal to 0.2 and less than or equal to 3, thereby a thickness uniformity of the backside-metal layer is improved.

Abstract: A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period; a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.

Abstract: An apparatus is disclosed that comprises a first structure configured to be connected to a chassis, a second structure configured to be attached to the first structure, the second structure including at least one first connector and a damper disposed between the first structure and the second structure, the damper configured to allow the second structure to move in one dimension relative to the first structure when the first connector is moved in a direction to be coupled to a second connector that is not aligned with the first connector.

Abstract: A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.

Abstract: A controlling circuit for ring oscillator is provided. First and second transistors of a first conductive type are coupled in series and between a node and a first power source. Third and fourth transistors of a second conductive type are coupled in parallel and between the node and a second power source. The node is coupled to a delay chain of the ring oscillator. The second and third transistors form a pseudo pass-gate inverter. An input of the pseudo pass-gate inverter is configured to receive an output signal of the delay chain. The first and fourth transistors are controlled by a realignment signal. When the realignment signal is in a realignment state, the first transistor is turned off and the fourth transistor is turned on, and when the realignment signal is in a normal state, the first transistor is turned on and the fourth transistor is turned off.

Abstract: Systems, methods, and devices for fractional realignment are disclosed herein. A feedback divider generates a feedback dividing clock signal based on a controlling oscillator frequency. A delta-sigma modulator is coupled to the feedback divider and generates a dividing ratio to the feedback divider. An accumulating phase adjustor is coupled to the delta-sigma modulator and (i) determines a difference between a frequency tuning word (FCW) and the dividing ratio and (ii) generates a coarse tuning word and a fine tuning word. A digital-to-time converter (DTC) is coupled to the accumulating phase adjustor and generates a first clock frequency based on a reference clock frequency, the coarse tuning word and the fine tuning word. A realignment pulse generator is coupled to the DTC and generates a realignment clock based on the first clock frequency having a period that is the same as a period of the controlling oscillator frequency.

Abstract: A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.

Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operational mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operational mode of the hybrid PLL.

Abstract: An apparatus is disclosed that comprises a first structure configured to be connected to a chassis, a second structure configured to be attached to the first structure, the second structure including at least one first connector and a damper disposed between the first structure and the second structure, the damper configured to allow the second structure to move in one dimension relative to the first structure when the first connector is moved in a direction to be coupled to a second connector that is not aligned with the first connector.

Abstract: The present invention provides a radioactive labeling method for neuropeptide Y (NPY) compound and a mammalian diagnostic radioactive targeting medicine with NPY peptide being modified at position 27th to 36th, and after binding with the chelating agent and labeling the radiation nucleus 66Ga, 67Ga, 68Ga, 177Lu or 111In to provide a radioactive targeting medicine for multi-type breast cancer diagnosis and treatment.

Abstract: An information handling system may include one or more illuminable icons to present information to a user of the system, such as information regarding a status of the information handling system. An illuminable icon may be lit by a plurality of light sources, and light from the plurality of light sources may be diffused across the illuminable icon by a light guide film. Some illuminable icons may have multiple portions that may be separately illuminated to convey different information to a user. An isolation block may prevent light from light sources configured to illuminate one portion of an illuminable icon from illuminating other portions of the illuminable icon. Thus, light for illuminating icons of an information handling system may be diffused and/or blocked to enhance aesthetic appeal of the icons and to prevent user confusion that may result from bleeding of light from one portion of an illuminable icon to another and/or uneven illumination of an icon.

Abstract: A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.

Abstract: A radioactive labeled long-acting peptide-targeting pharmaceutical and production method, in which the peptide targeted pharmaceutical is firstly dissolved in a solution, followed by labeling the radioactive at a high temperature, and the dosage of the pharmaceutical with radioactive labeling is expected to be reduced and labeling efficiency is improved, and no further purification by filtration is required, which shortens the preparation process and reduces personnel exposure in the working environment. The radioactive labeled long-acting peptide-targeting pharmaceutical can increase the specific binding capacity of tumors and reduce the non-specific accumulation in normal tissues. It can be applied to the field of tumor and nuclear medicine for diagnosis and treatment of tumors and/or tumor metastases with efficacy and precision treatment.

Abstract: An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (??) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ?? TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ?? TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ?? TDC, wherein the MASH type high-order ?? TDC is configured to measure the phase noise of a device under text (DUT).

Abstract: A frequency divider circuit includes a counter configured to generate a counter signal responsive to a frequency of a clock signal and a frequency ratio, and a compensation circuit coupled to the counter, and configured to generate an output signal. The output signal has a frequency equal to the frequency of the clock signal divided by a frequency ratio, and a duty cycle greater than 1/r, where r is the frequency ratio.

Abstract: A controlling circuit for ring oscillator is provided. First and second transistors of a first conductive type are coupled in series and between a node and a first power source. Third and fourth transistors of a second conductive type are coupled in parallel and between the node and a second power source. The node is coupled to a delay chain of the ring oscillator. The second and third transistors form a pseudo pass-gate inverter. An input of the pseudo pass-gate inverter is configured to receive an output signal of the delay chain. The first and fourth transistors are controlled by a realignment signal. When the realignment signal is in a realignment state, the first transistor is turned off and the fourth transistor is turned on, and when the realignment signal is in a normal state, the first transistor is turned on and the fourth transistor is turned off.

Abstract: Phase-locked loops (PLLs) are provided. A PLL includes a voltage-controlled oscillator (VCO), a frequency divider, a track-and-hold charge pump, and a frequency tracking circuit. The VCO is configured to provide an output clock corresponding to a pumping current. The frequency divider is configured to divide the output clock to provide a feedback signal. The track-and-hold charge pump is configured to provide the pumping current according to a reference clock and the feedback signal. The frequency tracking circuit is configured to decrease frequency error between the feedback signal and the reference clock. The track-and-hold charge pump includes a pumping switch and a pulse width modulator (PWM). The PWM is configured to provide a PWM signal to control the pumping switch according to the reference clock, so as to provide the pumping current corresponding to the feedback signal.

Abstract: An apparatus is disclosed that comprises a first structure configured to be connected to a chassis, a second structure configured to be attached to the first structure, the second structure including at least one first connector and a damper disposed between the first structure and the second structure, the damper configured to allow the second structure to move in one dimension relative to the first structure when the first connector is moved in a direction to be coupled to a second connector that is not aligned with the first connector.