Abstract: A trajectory prediction system for predicting a point of impact of an object shot from a ballistic device is provided. The trajectory prediction system includes an objective lens, an eyepiece lens optically coupled with the objective lens, an image sensor, a processor, and a display electrically connected to the processor and the image sensor. The image sensor, the processor, and the display are disposed between the objective lens and the eyepiece lens. When an external light reaches the image sensor through the objective lens, the image sensor transmits a first signal to the display, and the display shows an image according to the first signal. The processor calculates the trajectory of the object and transmits a second signal to the display, and the display simultaneously shows the image and at least one predictive point of impact according to the first and second signals.

Abstract: A driver circuit for receiving input data and generating an output signal to a termination element is provided, wherein the input data has a first bit and second bit, and the driver circuit includes: a pair of differential output terminals for outputting the output signal, wherein the pair of differential output terminals has a first output terminal and a second output terminal; at least one current mode drive unit, coupled to the pair of differential output terminals, for outputting a current from one of the first output terminal and the second output terminal, and receiving the current from the other of the first output terminal and the second output terminal according to the first bit; and at least one voltage mode drive unit, coupled to the pair of differential output terminals, for providing voltages to the first output terminal and the second output terminal according to the second bit.

Abstract: A driver circuit for receiving input data and generating an output signal to a termination element is disclosed, wherein the input data has a first bit and second bit, and the driver circuit includes: a pair of differential output terminals, arranged for outputting the output signal, wherein the pair of differential output terminals has a first output terminal and a second output terminal; a current mode drive unit, coupled to the pair of differential output terminals, for outputting a current from one of the first output terminal and the second output terminal, and receiving the current from the other of the first output terminal and the second output terminal according to the first bit; and a voltage mode drive unit, coupled to the pair of differential output terminals, for providing voltages to the first output terminal and the second output terminal according to at least the second bit.

Abstract: A method for performing data sampling control in an electronic device and an associated apparatus are provided, where the method includes the steps of: detecting whether a data pattern of a received signal of a decision feedback equalizer (DFE) receiver in the electronic device matches a predetermined data pattern, to selectively trigger a data sampling time shift configuration of the DFE receiver; and when the data sampling time shift configuration is triggered, utilizing a phase shift clock, rather than a normal clock corresponding to a normal configuration of the DFE receiver, as an edge sampler clock of an edge sampler in the DFE receiver, to lock onto edge timing of the received signal, and controlling the phase shift clock and the normal clock to have different phases, respectively, to shift data sampling time of the DFE receiver, for performing data sampling in the DFE receiver.

Abstract: A method for performing loop unrolled decision feedback equalization (DFE) and an associated apparatus are provided.

Abstract: A method for performing data sampling control in an electronic device and an associated apparatus are provided, where the method includes the steps of: detecting whether a data pattern of a received signal of a decision feedback equalizer (DFE) receiver in the electronic device matches a predetermined data pattern, to selectively trigger a data sampling time shift configuration of the DFE receiver; and when the data sampling time shift configuration is triggered, utilizing a phase shift clock, rather than a normal clock corresponding to a normal configuration of the DFE receiver, as an edge sampler clock of an edge sampler in the DFE receiver, to lock onto edge timing of the received signal, and controlling the phase shift clock and the normal clock to have different phases, respectively, to shift data sampling time of the DFE receiver, for performing data sampling in the DFE receiver.

Abstract: A method of forming a semiconductor memory storage device that includes forming first and second doped regions of a first type in a semiconductor substrate and laterally spaced from one another, forming a gate dielectric extends over the semiconductor substrate between the first and second doped regions, forming a floating gate on the gate dielectric, and forming an ultraviolet (UV) light blocking material vertically disposed above the floating gate such that the floating gate remains electrically charged after the semiconductor memory storage device is exposed to UV light.

Abstract: A stacked structure comprises a semiconductor chip which includes a substrate having at least one substrate via hole penetrating through the substrate; at least one backside metal layer formed on a backside of the substrate covering an inner surface of the substrate via hole and at least part of the backside of the substrate; at least one front-side metal layer formed on the front-side of the substrate and electrically connected to the at least one backside metal layer on a top of at least one of the at least one substrate via hole; at least one electronic device formed on the front-side of the substrate and electrically connected to the at least one front-side metal layer; and at least one metal bump formed on at least one of the backside metal layer and the front-side metal layer.

Abstract: A sight and methods of operation thereof are provided. In some embodiments, an image is captured via an image capture unit, and a center position is calculated according to the positions of at least three impact points in the image, and a predefined view center of a display unit is set to the center position. In some embodiments, an angle of dip of the sight to a plane is detected via a dip angle detector. A predictive impact point is calculated according to the angle of dip and at least one calculation parameter, and an impact point indication is accordingly displayed in the display unit. When the angle of dip is changed, the predictive impact point is recalculated according to the new angle of dip, and the corresponding impact point indication is displayed.

Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including mounting a die to a top surface of a substrate to form a device, encapsulating the die and top surface of the substrate in a mold compound, the mold compound having a first thickness over the die, and removing a portion, but not all, of the thickness of the mold compound over the die. The method further includes performing further processing on the device, and removing the remaining thickness of the mold compound over the die.

Abstract: A structure of a semiconductor chip with substrate via holes and metal bumps and a fabrication method thereof. The structure comprises a substrate, at least one backside metal layer, at least one first metal layer, at least one electronic device, and at least one metal bump. The substrate has at least one substrate via hole penetrating through the substrate. The at least one first metal layer and electronic device are formed on the front side of the substrate. The at least one metal bump is formed on the at least one first metal layer. The at least one backside metal layer is formed on the backside of the substrate covering the inner surface of the substrate via hole and at least part of the backside of the substrate and connected to the first metal layer on the top of the substrate via hole.

Abstract: A semiconductor memory storage device includes first and second doped regions of a first type disposed in a semiconductor substrate. The first and second doped regions of the first type being laterally spaced from one another. A gate dielectric extends over the semiconductor substrate between the first and second doped regions, and a floating gate is disposed on the gate dielectric. An ultraviolet (UV) light blocking material is vertically disposed above the floating gate and has a size that covers the floating gate such that the floating gate remains electrically charged after the semiconductor memory storage device is exposed to UV light.

Abstract: A method of shielding through silicon vias (TSVs) in a passive interposer includes doping a substrate with positive ions, and implanting positive ions in an upper portion of the substrate, such that the substrate has at least a p-doped portion and a heavily p-doped upper portion. The method further includes forming an interlayer dielectric (ILD) above the heavily p-doped upper portion. The method further includes forming a plurality of through silicon vias (TSVs) through the ILD and the substrate, such that the passive interposer is configured to electrically couple at least one structure above and below the passive interposer. The method further includes forming, between pairs of TSVs of the plurality of TSVs, a plurality of shielding lines through the interlayer dielectric, the shielding lines configured to electrically couple the heavily p-doped upper portion of the substrate and at least one interconnect structure above the ILD.

Abstract: A method of testing a three-dimensional integrated circuit (3DIC) includes applying a voltage through at least one testing element and at least one conductive line, wherein the at least one conductive line traces a perimeter of at least one of a top chip or an interposer substantially parallel to an outer edge of the at least one top chip or the interposer, and the at least one conductive line is configured to electrically connect a plurality of conductive connectors. The method further includes measuring a current responsive to the applied voltage. The method further includes determining an integrity of the 3DIC based on the measured current.

Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including mounting a die to a top surface of a substrate to form a device, encapsulating the die and top surface of the substrate in a mold compound, the mold compound having a first thickness over the die, and removing a portion, but not all, of the thickness of the mold compound over the die. The method further includes performing further processing on the device, and removing the remaining thickness of the mold compound over the die.

Abstract: A semiconductor device includes a first die having a first active surface and a first backside surface opposite the first active surface, a second die having a second active surface and a second backside surface opposite the second active surface, and an interposer, the first active surface of the first die being electrically coupled to a first side of the interposer, the second active surface of the second die being electrically coupled to a second side of the interposer. The semiconductor device also includes a first connector over the interposer, a first encapsulating material surrounding the second die, the first encapsulating material having a first surface over the interposer, and a via electrically coupling the first connector and the interposer. A first end of the via is substantially coplanar with the first surface of the first encapsulating material.

Abstract: A three-dimensional integrated circuit (3DIC) including a top chip having at least one active device and an interposer having conductive routing layers and vias. The 3DIC further includes a plurality of conductive connectors configured to electrically connect the top chip and the interposer. The 3DIC further includes a conductive line over at least one of the top chip or the interposer. The conductive line traces a perimeter of top chip or interposer parallel to an outer edge of the top chip or interposer. The conductive line is configured to electrically connect the conductive connectors. The 3DIC further includes at least one testing element over at least one of the top chip or the interposer. The testing element is configured to electrically connect to the plurality of conductive connectors.

Abstract: A method of forming an integrated circuit includes providing a semiconductor substrate, forming a metallization layer over the semiconductor substrate, wherein the metallization layer comprises a metal feature in a low-k dielectric layer and extending from a top surface of the low-k dielectric layer into the low-k dielectric layer, performing a treatment to the low-k dielectric layer to form a hydrophilic top surface, and plating a cap layer on the metal feature in a solution.

Abstract: In a process, at least one circuit element is formed in a substrate. A conductive layer is formed over the substrate and in electrical contact with the at least one circuit element. Electrostatic charges are discharged from the substrate via the conductive layer.

Abstract: A sight and methods of operation thereof are provided. In some embodiments, an image is captured via an image capture unit, and a center position is calculated according to the positions of at least three impact points in the image, and a predefined view center of a display unit is set to the center position. In some embodiments, an angle of dip of the sight to a plane is detected via a dip angle detector. A predictive impact point is calculated according to the angle of dip and at least one calculation parameter, and an impact point indication is accordingly displayed in the display unit. When the angle of dip is changed, the predictive impact point is recalculated according to the new angle of dip, and the corresponding impact point indication is displayed.