Abstract: A memory device includes a plurality of memory cells disposed over a substrate and formed as an array that has a plurality of rows and a plurality of columns. Each of the plurality of memory cells includes a plurality of transistors. A first subset of the plurality of memory cells, that are disposed in first neighboring ones of the plurality of rows, are physically coupled to a corresponding one of a plurality of second interconnect structures that carries a supply voltage through a corresponding one of a plurality of first interconnect structures. The plurality of first interconnect structures extend along a first lateral direction in parallel with a lengthwise direction of a channel of each of the transistors of the memory cells, and the plurality of second interconnect structures, disposed above the plurality of first interconnect structures, extend along a second lateral direction perpendicular to the first lateral direction.

Abstract: A liquid crystal polymer, composition, liquid crystal polymer film, laminated material and method of forming liquid crystal polymer film are provided. The liquid crystal polymer includes a first repeating unit, a second repeating unit, a third repeating unit, and a fourth repeating unit. The first repeating unit has a structure of Formula (I), the second repeating unit has a structure of Formula (II), the third repeating unit has a structure of Formula (III), and the fourth repeating unit has a structure of Formula (IV), a structure of Formula (V) or a structure of Formula (VI) wherein A1, A2, A3, Z1, R1, R2, R3 and Q are as defined in the specification.

Abstract: A throttle control method for a mobile device include collecting input data, generating a first set of user experience indices according to the input data, and checking whether a user experience index of the first set of user experience indices satisfies a UEI threshold. The input data includes common information data, current configuration data and a plurality of throttle control parameters. Each user experience index of the first set of user experience indices is corresponding to at least one of throttle control parameter of the plurality of throttle control parameters.

Abstract: Disclosed herein are related to a memory device. In one aspect, a memory device includes a set of memory cells. In one aspect, the memory device includes a first bit line extending along a direction. The first bit line may be coupled to a subset of the set of memory cells disposed along the direction. In one aspect, the memory device includes a second bit line extending along the direction. In one aspect, the memory device includes a switch coupled between the first bit line and the second bit line.

Abstract: The present invention provides a circuitry of a biopotential acquisition system, where the circuitry includes an input node, an ETI transmitter, a capacitor and an ETI receiver. The input node is configured to receive an input signal from an electrode of the biopotential acquisition system. The ETI transmitter is configured to generate a transmitter signal. A first node of the capacitor is coupled to the ETI transmitter, and a second node of the capacitor is coupled to the input node. The ETI receiver is coupled to the input node, and is configured to receive the transmitter signal via the capacitor to generate an ETI.

Abstract: A semiconductor device, includes a first metal layer, a second metal layer, a drain/source contact and at least one conductive via. The first metal layer has a first conductor that extends in a first direction and a second conductor that extends in the first direction, wherein the second conductor is directly adjacent to the first conductor. The second metal layer has a third conductor that extends in a second direction, wherein the second direction is transverse to the first direction. The drain/source contact extends in the second direction and is connected to the second conductor. The at least one conductive via connects the first conductor and the second conductor through the third conductor.

Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.

Abstract: An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.

Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

Abstract: A transmission interface between at least a first module and a second module is proposed. The transmission interface includes at least two physical transmission mediums. Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated. The at least two physical transmission mediums include a first physical transmission medium arranged to carry a first multiplexed signal including a first IF signal and a reference clock signal. The first IF signal and the reference clock signal are at different frequencies.

Abstract: A memory device and a method for operating the memory device are provided. The memory device includes a memory cell and a bit line connected to the memory cell. A negative voltage generator is connected to the bit line. The negative voltage generator, when enabled, is operative to provide a first write path for the bit line. A control circuit is connected to the negative voltage generator and the bit line. The control circuit is operative to provide a second write path for the bit line when the negative voltage generator is not enabled.

Abstract: A package structure and method for forming the same are provided. The package structure includes a first through via structure formed in a substrate and a semiconductor die formed below the first through via structure. The package structure further includes a conductive structure formed in a passivation layer over the substrate. The conductive structure includes a first via portion and a second via portion, the first via portion is directly over the first through via structure, and there is no conductive material directly below and in direct contact with the second via portion.

Abstract: Semiconductor structures and methods for forming the same are provided. A method according to the present disclosure includes forming active regions on a substrate, forming an interconnect structure over the active regions, the interconnect structure including a plurality of dielectric layers and a guard ring disposed within the dielectric layers, etching an opening through the interconnect structure and at least a first portion of the active regions, the opening extending into the substrate, and forming a via structure within the opening. The via structure is surrounded by the guard ring when viewed along a direction perpendicular to a top surface of the substrate.

Abstract: Present disclosure provides a semiconductor structure, including a semiconductor fin having a first portion and a second portion over the first portion, a first conductive region abutting a first lateral surface of the first portion and a first lateral surface of the second portion, a metal gate having a bottom portion and an upper portion, the bottom portion being between the first portion and the second portion of the semiconductor fin, and the upper portion being over the second portion of the semiconductor fin, and a first spacer between the bottom portion of the metal gate and the first conductive region. A method for manufacturing the semiconductor structure described herein is also provided.

Abstract: This disclosure is related to an ultraviolet fluid sterilizing box structure. A box (10) includes a chamber (100), a water inlet (101) and a water outlet (102). The water inlet (101) and the water outlet (102) are located on different sides of the box (10). The partition (20) is disposed in the chamber (100) and includes an outer cylinder (21) and an inner cylinder (22). The outer cylinder (21) includes an outer cavity (210) and an inflow inlet (211). The inner cylinder (22) includes an inner cavity (220) and an opening (221). The ultraviolet module (30) is disposed on one side of the box (10) and includes a light-transmitting plate (31) and an ultraviolet lamp set (32). The light-transmitting plate (31) seals the outer cylinder (21). The ultraviolet rays irradiate the inner cavity (220) and the outer cavity (210).

Abstract: A food temperature measuring device includes a device main body, a signal control module, a temperature measuring module, a light emitting display module, and an information display module. The temperature measuring module is configured for measuring a predetermined food so as to obtain measured temperature information of the predetermined food. The light emitting display module includes a first light emitting unit for providing a first food light message, a second light emitting unit for providing a second food light message, and a third light emitting unit for providing a third food light message. The information display module is configured for displaying a measured temperature value of the measured temperature information obtained by the temperature measuring module. Therefore, the light emitting display module can be configured for providing food category corresponding information corresponding to the predetermined food according to the first, the second, and the third food light message.

Abstract: The present invention provides a circuit applied to a biopotential acquisition system, wherein the circuit includes an active current source and an amplifier. In the operations of the circuit, the active current source is configured to provide a current to two input terminals of the circuit, wherein the two input terminals of the circuit are coupled to two input electrodes of the biopotential acquisition system; and the amplifier is configured to receive input signals from the two input terminals to generate an output signal.

Abstract: The present invention provides a circuit applied to a bio-information acquisition system, wherein the circuit includes a terminal, an output circuit, a feedback circuit and a calibration circuit. In the operations of the circuit, the terminal is arranged to receive an input signal, the output circuit is configured to generate an output signal according to the input signal, the feedback circuit is configured to receive the output signal to generate a current signal to the terminal, and the calibration circuit is configured to generate a control signal to control the feedback circuit to determine a level of the current signal according to the output signal.

Abstract: The present invention provides a lead-on detection circuitry of a biopotential acquisition system. The lead-on detection circuitry includes an input terminal, a duty-cycle controller, a transmitting signal generator and a mixer-based receiver. The duty-cycle controller is configured to generate a first clock signal. The transmitting signal generator is configured to generate a transmitting signal to the input terminal according to the first clock signal. The mixer-based receiver is configured to perform a mixing operation based on the first clock signal and the transmitting signal to generate an output signal, wherein the output signal indicates if an electrode of the biopotential acquisition system is in contact with a human body, and the electrode is coupled to the input terminal.

Abstract: An improved USB charging apparatus includes a main body and a plurality of power processing modules arranged in the main body; each one of the power processing modules having two USB charging ports connected thereto, and the two USB charging ports configured to be a first charging port and a second charging port having specifications different from each other; the first charging port and the second charging port arranged adjacent to each other; each one of the power processing modules further comprising a detection control circuit and a switch circuit, allowing each charging circuit to be provided with the charging ports of two types of specifications, such that user can choose one of the charging ports for use depending upon the actual needs. Accordingly, the improved USB charging apparatus is not limited to certain specifications of charging ports only, thereby increasing the use significantly.