Patents by Inventor Chih-Hsin Chen

Chih-Hsin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210287746
    Abstract: A memory cell array of a multi-time programmable non-volatile memory includes plural memory cells. The memory cell has the structure of 1T1C cell, 2T1C cell or 3T1C cell. Moreover, the floating gate transistors of the memory cells in different rows of the memory cell array are constructed in the same well region. Consequently, the chip size is reduced. Moreover, by providing proper bias voltages to the memory cell array, the program action, the erase action or the read action can be performed normally.
    Type: Application
    Filed: February 24, 2021
    Publication date: September 16, 2021
    Inventors: Chih-Hsin CHEN, Chun-Yuan LO, Shih-Chen WANG, Tsung-Mu LAI
  • Patent number: 11119001
    Abstract: A machine tool health monitoring method which is to use a predetermined plurality of vibration sensors on a plurality of components of a machine tool and to drive motors of the machine tool to excite the machine tool using an electronic device while the health status of the machine tool is good, and then to perform a diagnostic process to obtain a characteristic cluster consisting of a plurality of modals, and then to define the characteristic cluster as a sample health characteristic cluster. The diagnostic process includes the procedures of vibration transmissibility obtaining, singular value decomposition, curve fitting and modal establishing. In addition, excite the machine tool and proceed the diagnosis process to obtain a current health characteristic cluster. Finally, the current health characteristic cluster is compared with the sample health characteristic cluster to judge whether the machine tool is healthy or not.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: September 14, 2021
    Assignees: NATIONAL CHUNG CHENG UNIVERSITY, TONGTAI MACHINE & TOOL CO., LTD.
    Inventors: Chih-Chun Cheng, Yu-Sheng Chiu, Wen-Nan Cheng, Ping-Chun Tsai, Yu-Hsin Kuo, Wei-Jen Chen, De-Shin Liu, Chen-Wei Chuang, Chih-Ta Wu, Wen-Peng Tseng, Wen-Chieh Kuo
  • Publication number: 20210272849
    Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 2, 2021
    Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 11106000
    Abstract: A driving mechanism for supporting an optical member is provided, including a base, a frame, a movable portion, a driving module, and an adhesive member. The base includes a plurality of first sidewalls, and at least one recess is formed on the first sidewalls. The frame includes a plurality of second sidewalls, and at least one opening is formed on the second sidewalls. The base and the frame form a hollow box, and the opening corresponds to the recess. The movable portion and the driving module are disposed in the hollow box. The driving module can drive the movable portion to move relative to the base. The adhesive member is accommodated in the opening and the recess, and extended along the first sidewalls. The adhesive member is disposed between the first sidewalls and the second sidewalls.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: August 31, 2021
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Bing-Ru Song, Yi-Ho Chen, Chia-Pin Hsu, Chih-Wei Weng, Shin-Hua Chen, Chien-Lun Huang, Chao-Chun Chang, Shou-Jen Liu, Kun-Shih Lin, Nai-Wen Hsu, Yu-Cheng Lin, Shang-Yu Hsu, Yu-Huai Liao, Yi-Hsin Nieh, Shih-Ting Huang, Kuo-Chun Kao, Fu-Yuan Wu
  • Publication number: 20210226764
    Abstract: The present invention provides a lead-on detection circuitry of a biopotential acquisition system. The lead-on detection circuitry includes an input terminal, a duty-cycle controller, a transmitting signal generator and a mixer-based receiver. The duty-cycle controller is configured to generate a first clock signal. The transmitting signal generator is configured to generate a transmitting signal to the input terminal according to the first clock signal. The mixer-based receiver is configured to perform a mixing operation based on the first clock signal and the transmitting signal to generate an output signal, wherein the output signal indicates if an electrode of the biopotential acquisition system is in contact with a human body, and the electrode is coupled to the input terminal.
    Type: Application
    Filed: December 3, 2020
    Publication date: July 22, 2021
    Inventor: Chih-Hsin Chen
  • Patent number: 11063772
    Abstract: A multi-cell per bit nonvolatile memory (NVM) unit includes a select transistor disposed on a first oxide define (OD) region, a word line transistor disposed on the first OD region, and serially connected floating gate transistors disposed between the select transistor and the word line transistor. A first floating gate extension continuously extends toward a second OD region and adjacent to an erase gate region. A second floating gate extension continuously extends toward a third OD region and is capacitively coupled to a control gate region. A channel length of each of the floating gate transistors is shorter than that of the select transistor or the word line transistor.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: July 13, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Chih-Hsin Chen, Tsung-Mu Lai, Shih-Chen Wang
  • Patent number: 11062773
    Abstract: A near-memory computation system includes a plurality of computation nodes. Each computation node receives a plurality of input signals and outputs a computing result signal. The computation node includes a plurality of non-volatile memory cells and a processing element. Each non-volatile memory cell stores a weighting value during a program operation and outputs a weighting signal according to the weighting value during a read operation. The processing element is coupled to the plurality of non-volatile memory cells. The processing element receives the plurality of input signals and generates the computing result signal by performing computations with the plurality of input signals and a plurality of weighting signals generated by the plurality of non-volatile memory cells. The plurality of non-volatile memory cells and the processing element are manufactured by different or the same processes.
    Type: Grant
    Filed: March 22, 2020
    Date of Patent: July 13, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Chun-Fu Lin, Ching-Yuan Lin, Tsung-Mu Lai, Chih-Hsin Chen
  • Patent number: 11017862
    Abstract: A multi-time programming memory cell includes a floating gate transistor, a first capacitor, a second capacitor and a third capacitor. The floating gate transistor has a floating gate. A first terminal of the floating gate transistor is coupled to a source line. A second terminal of the floating gate transistor is coupled to a bit line. A first terminal of the first capacitor is connected with the floating gate. A second terminal of the first capacitor is connected with an erase line. A first terminal of the second capacitor is connected with the floating gate. A second terminal of the second capacitor is connected with a control line. A first terminal of the third capacitor is connected with the floating gate. A second terminal of the third capacitor is connected with an inhibit line.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: May 25, 2021
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Chih-Hsin Chen
  • Patent number: 10991430
    Abstract: A non-volatile memory cell includes a storage transistor having a first terminal, a second terminal, and a gate terminal. During a program operation, the first terminal of the storage transistor receives a data voltage according to a weighting to be stored in the non-volatile memory cell, the second terminal of the storage transistor is floating, and the gate terminal of the storage transistor is coupled to a program voltage. The program voltage is greater than the data voltage.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 27, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Tsung-Mu Lai, Chih-Hsin Chen, Chun-Fu Lin
  • Publication number: 20210074855
    Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.
    Type: Application
    Filed: September 8, 2020
    Publication date: March 11, 2021
    Inventors: Chih-Hsin Chen, Shih-Chen Wang, Tsung-Mu Lai, Wen-Hao Ching, Chun-Yuan Lo, Wei-Chen Chang
  • Patent number: 10910062
    Abstract: A random bit cell includes a latch and a nonvolatile memory cell. The nonvolatile memory cell includes a storage circuit, a control element, an erase element, and a read circuit. The storage circuit is coupled to a first terminal of the latch. The storage circuit includes a floating gate transistor having a first terminal, a second terminal, and a floating gate. The control element has a first terminal coupled to a control line, and a control terminal coupled to the floating gate of the floating gate transistor. The erase element has a first terminal coupled to an erase line, and a control terminal coupled to the floating gate of the floating gate transistor. The read circuit is coupled to a bit line, a select gate line, and the floating gate of the floating gate transistor.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: February 2, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Tsung-Mu Lai, Hung-Hsiang Wang, Cheng-Te Yang, Chih-Hsin Chen
  • Publication number: 20200365209
    Abstract: A near-memory computation system includes a plurality of computation nodes. Each computation node receives a plurality of input signals and outputs a computing result signal. The computation node includes a plurality of non-volatile memory cells and a processing element. Each non-volatile memory cell stores a weighting value during a program operation and outputs a weighting signal according to the weighting value during a read operation. The processing element is coupled to the plurality of non-volatile memory cells. The processing element receives the plurality of input signals and generates the computing result signal by perform computations with the plurality of input signals and a plurality of weighting signals generated by the plurality of non-volatile memory cells. The plurality of non-volatile memory cells and the processing element are manufactured by different or the same processes.
    Type: Application
    Filed: March 22, 2020
    Publication date: November 19, 2020
    Inventors: Chun-Fu Lin, Ching-Yuan Lin, Tsung-Mu Lai, Chih-Hsin Chen
  • Publication number: 20200258579
    Abstract: A random bit cell includes a latch and a nonvolatile memory cell. The nonvolatile memory cell includes a storage circuit, a control element, an erase element, and a read circuit. The storage circuit is coupled to a first terminal of the latch. The storage circuit includes a floating gate transistor having a first terminal, a second terminal, and a floating gate. The control element has a first terminal coupled to a control line, and a control terminal coupled to the floating gate of the floating gate transistor. The erase element has a first terminal coupled to an erase line, and a control terminal coupled to the floating gate of the floating gate transistor. The read circuit is coupled to a bit line, a select gate line, and the floating gate of the floating gate transistor.
    Type: Application
    Filed: November 27, 2019
    Publication date: August 13, 2020
    Inventors: Tsung-Mu Lai, Hung-Hsiang Wang, Cheng-Te Yang, Chih-Hsin Chen
  • Patent number: 10725001
    Abstract: A liquid crystal composition includes a nematic liquid crystal, and a compound of Formula (I) where R is an alkyl, aryl, aralkyl or heteroaryl having 6 to 30 carbon atoms, wherein the compound accounts for 0.3 to 0.6% of the liquid crystal composition. Further, a sensing device includes a substrate, a frame, an alignment film, the liquid crystal composition as described above, and two polarizers. The frame is connected to the substrate and forms an accommodation space having an opening, and the alignment film and the liquid crystal composition are both located inside the accommodation space. One of the polarizers is arranged in correspondence with the opening such that a channel exists between the polarizer and the frame, the other polarizer is located at a lateral side of the substrate, and the polarization directions of the two polarizers intersect with each other.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: July 28, 2020
    Assignee: TAMKANG UNIVERSITY
    Inventors: Chih-Hsin Chen, Wei-Long Chen, Tsung-Yang Ho
  • Publication number: 20200202941
    Abstract: A non-volatile memory cell includes a storage transistor having a first terminal, a second terminal, and a gate terminal. During a program operation, the first terminal of the storage transistor receives a data voltage according to a weighting to be stored in the non-volatile memory cell, the second terminal of the storage transistor is floating, and the gate terminal of the storage transistor is coupled to a program voltage. The program voltage is greater than the data voltage.
    Type: Application
    Filed: October 30, 2019
    Publication date: June 25, 2020
    Inventors: Tsung-Mu Lai, Chih-Hsin Chen, Chun-Fu Lin
  • Publication number: 20200194079
    Abstract: A multi-time programming memory cell includes a floating gate transistor, a first capacitor, a second capacitor and a third capacitor. The floating gate transistor has a floating gate. A first terminal of the floating gate transistor is coupled to a source line. A second terminal of the floating gate transistor is coupled to a bit line. A first terminal of the first capacitor is connected with the floating gate. A second terminal of the first capacitor is connected with an erase line. A first terminal of the second capacitor is connected with the floating gate. A second terminal of the second capacitor is connected with a control line. A first terminal of the third capacitor is connected with the floating gate. A second terminal of the third capacitor is connected with an inhibit line.
    Type: Application
    Filed: October 23, 2019
    Publication date: June 18, 2020
    Inventor: Chih-Hsin Chen
  • Publication number: 20200163574
    Abstract: The present invention provides a circuit applied to a biopotential acquisition system, wherein the circuit includes an active current source and an amplifier. In the operations of the circuit, the active current source is configured to provide a current to two input terminals of the circuit, wherein the two input terminals of the circuit are coupled to two input electrodes of the biopotential acquisition system; and the amplifier is configured to receive input signals from the two input terminals to generate an output signal.
    Type: Application
    Filed: November 12, 2019
    Publication date: May 28, 2020
    Inventor: Chih-Hsin Chen
  • Publication number: 20200163577
    Abstract: The present invention provides a circuit applied to a bio-information acquisition system, wherein the circuit includes a terminal, an output circuit, a feedback circuit and a calibration circuit. In the operations of the circuit, the terminal is arranged to receive an input signal, the output circuit is configured to generate an output signal according to the input signal, the feedback circuit is configured to receive the output signal to generate a current signal to the terminal, and the calibration circuit is configured to generate a control signal to control the feedback circuit to determine a level of the current signal according to the output signal.
    Type: Application
    Filed: November 12, 2019
    Publication date: May 28, 2020
    Inventors: Chih-Hsin Chen, Yu-Hung Lin
  • Patent number: 10642579
    Abstract: A non-volatile memory includes a memory cell. A storage element of the memory cell has following structures. A first floating gate transistor includes a first floating gate, a first source/drain terminal and a second source/drain terminal. A second floating gate transistor includes the first floating gate, a third source/drain terminal and a fourth source/drain terminal. A third floating gate transistor includes a second floating gate, a fifth source/drain terminal and a sixth source/drain terminal. A fourth floating gate transistor includes the second floating gate, a seventh source/drain terminal and an eighth source/drain terminal. The first and third source/drain terminals are connected with a first terminal of the storage element. The second and fifth source/drain terminals are connected with each other. The fourth and seventh source/drain terminals are connected with each other. The sixth and eighth source/drain terminals are connected with a second terminal of the storage element.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: May 5, 2020
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chih-Hsin Chen, Shih-Chen Wang
  • Publication number: 20200079915
    Abstract: The invention relates to a method for preparing a polymer gel film containing liquid crystal droplets, comprising the steps of: preparing liquid crystal droplets containing a ligand, by adding a nematic liquid crystal containing a ligand to an aqueous surfactant solution, and mixing, to obtain the liquid crystal droplets containing a ligand; adding the liquid crystal droplets containing a ligand to an aqueous polymer solution, and mixing, to obtain an aqueous polymer solution containing the liquid crystal droplets; and spreading the aqueous polymer solution containing the liquid crystal droplets flatly in a polymer container, and allowing the aqueous polymer solution containing the liquid crystal droplets to gelatinize, to obtain a polymer gel film containing liquid crystal droplets. The invention utilizes liquid crystal droplets dispersed in the agarose to detect mercuric ions in the water, and through the configuration change of the liquid crystal droplets, the mercuric ions is specifically detected.
    Type: Application
    Filed: July 11, 2019
    Publication date: March 12, 2020
    Inventors: CHIH-HSIN CHEN, JHIH-WEI HUANG, JUNG-JUNG CHANG