Patents by Inventor Chih-Hsin Chen

Chih-Hsin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11508627
    Abstract: A method includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; performing an operation on the substrate; removing the barrier layer from the first trench to expose the dielectric layer subsequent to the operation; and depositing a work function layer over the dielectric layer in the first trench.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Jing Lee, Ya-Yun Cheng, Hau-Yu Lin, I-Sheng Chen, Chia-Ming Hsu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 11502182
    Abstract: A semiconductor device includes a substrate. A gate structure is disposed over the substrate in a vertical direction. The gate structure extends in a first horizontal direction. An air spacer is disposed adjacent to a first portion of the gate structure in a second horizontal direction that is different from the first horizontal direction. The air spacer has a vertical boundary in a cross-sectional side view defined by the vertical direction and the first horizontal direction.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hsin Yang, Yen-Ming Chen, Feng-Cheng Yang, Tsung-Lin Lee, Wei-Yang Lee, Dian-Hau Chen
  • Patent number: 11497411
    Abstract: The present invention provides a circuit applied to a bio-information acquisition system, wherein the circuit includes a terminal, an output circuit, a feedback circuit and a calibration circuit. In the operations of the circuit, the terminal is arranged to receive an input signal, the output circuit is configured to generate an output signal according to the input signal, the feedback circuit is configured to receive the output signal to generate a current signal to the terminal, and the calibration circuit is configured to generate a control signal to control the feedback circuit to determine a level of the current signal according to the output signal.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: November 15, 2022
    Assignee: MEDIATEK INC.
    Inventors: Chih-Hsin Chen, Yu-Hung Lin
  • Publication number: 20220359002
    Abstract: A memory device includes a first word line and a second word line. A first portion of the first word line is formed in a first metal layer, a second portion of the first word line is formed in a second metal layer above the first metal layer, and a third portion of the first word line is formed in a third metal layer below the second metal layer. A first portion of the second word line is formed in the first metal layer. A second portion of the second word line is formed in the second metal layer. The first portion, the second portion, and the third portion of the first word line have sizes that are different from each other, and the first portion and the second portion of the second word line have sizes that are different from each other.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 10, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsin NIEN, Wei-Chang ZHAO, Chih-Yu LIN, Hidehiro FUJIWARA, Yen-Huei CHEN, Ru-Yu WANG
  • Patent number: 11486695
    Abstract: The present invention provides a measurement device for grinding wheel. One or more thickness measurement device is disposed slidably on a platform. A spinning device is disposed on the platform. A grinding wheel is fixed on the spinning device. The spinning shaft spins the grinding wheel. The one or more thickness measurement device measures the flatness condition of the grinding wheel. Furthermore, according to the present invention, a diameter measurement device is disposed inside the platform and measures the roundness of the outer periphery of the grinding wheel. Since the structure can be disassembled easily, the whole measurement device for grinding wheel can be carried conveniently. In addition, measurements can be performed by users on the site where the grinding wheel is located for real-timely understanding the real size and wear condition of grinding wheel.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: November 1, 2022
    Assignee: Metal Industries Research & Development Centre
    Inventors: Chin-Kang Chen, Ching-An Lin, Chia-Ho Cheng, Sung-Liang Hsieh, Chih-Hsin Chang
  • Patent number: 11482725
    Abstract: An electrode and a lithium-ion battery employing the electrode are provided. The electrode includes an active layer, a conductive layer, and a non-conductive layer. The conductive layer is disposed on the top surface of the active layer. The conductive layer includes a first porous film and a conductive lithiophilic material, and the conductive lithiophilic material is within the first porous film and covers the inner surface of the first porous film. The non-conductive layer includes a second porous film and a non-conductive lithiophilic material, and the non-conductive lithiophilic material is within the second porous film and covers the inner surface of the second porous film. The conductive layer is disposed between the active layer and the non-conductive layer. The binding energy (?G) of the lithiophilic material with lithium is less than or equal to ?2.6 eV.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: October 25, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Wei-Hsin Wu, Chih-Ching Chang, Yu Fang Huang, Li-Ju Chen, Chia-Chen Fang
  • Publication number: 20220328759
    Abstract: In a method of manufacturing a semiconductor device including a magnetic random access memory (MRAM) cell, a first layer made of a conductive material is formed over a substrate. A second layer for a magnetic tunnel junction (MTJ) stack is formed over the first conductive layer. A third layer is formed over the second layer. A first hard mask pattern is formed by patterning the third layer. The MTJ stack is formed by patterning the second layer by an etching operation using the first hard mask pattern as an etching mask. The etching operation stops at the first layer. A sidewall insulating layer is formed over the MTJ stack. After the sidewall insulating layer is formed, a bottom electrode is formed by patterning the first layer to form the MRAM cell including the bottom electrode, the MTj stack and the first hard mask pattern as an upper electrode.
    Type: Application
    Filed: September 29, 2021
    Publication date: October 13, 2022
    Inventors: Chih-Hsin YANG, Dian-Hau CHEN, Yen-Ming CHEN, Yu-Jen WANG, Chen-Chiu HUANG
  • Patent number: 11469781
    Abstract: A transmission interface between at least a master module and a slave module is proposed. The transmission interface includes a predetermined number of physical transmission medium(s). Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated, and the predetermined number is not smaller than a number of intermediate frequency (IF) stream(s) to be transmitted.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: October 11, 2022
    Assignee: MEDIATEK INC.
    Inventors: Chieh-Hsun Hsiao, Ming-Chou Wu, Wen-Chang Lee, Narayanan Baskaran, Wei-Hsin Tseng, Jenwei Ko, Po-Sen Tseng, Hsin-Hung Chen, Chih-Yuan Lin, Caiyi Wang
  • Publication number: 20220319818
    Abstract: An apparatus includes a processing chamber, a substrate support in the processing chamber, a plasma source coupled to the processing chamber, and a plurality of heating devices arranged on the processing chamber. Each heating device is configured to emit laser beam on a substrate positioned on the substrate support to heat the substrate.
    Type: Application
    Filed: March 31, 2021
    Publication date: October 6, 2022
    Inventors: Po-Ju CHEN, Cha-Hsin CHAO, Chih-Teng LIAO
  • Patent number: 11451366
    Abstract: The present invention provides a lead-on detection circuitry of a biopotential acquisition system. The lead-on detection circuitry includes an input terminal, a duty-cycle controller, a transmitting signal generator and a mixer-based receiver. The duty-cycle controller is configured to generate a first clock signal. The transmitting signal generator is configured to generate a transmitting signal to the input terminal according to the first clock signal. The mixer-based receiver is configured to perform a mixing operation based on the first clock signal and the transmitting signal to generate an output signal, wherein the output signal indicates if an electrode of the biopotential acquisition system is in contact with a human body, and the electrode is coupled to the input terminal.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: September 20, 2022
    Assignee: MEDIATEK INC.
    Inventor: Chih-Hsin Chen
  • Patent number: 11443542
    Abstract: A fingerprint recognition method is provided. The method includes obtaining a plurality of fingerprint images by sensing a finger of a user, respectively calculating geometric center points corresponding to the fingerprint images, and calculating positions and offsets of the fingerprint images according to the geometric center points. The method also includes filling signals in the fingerprint images into a part of pixels in a pixel array according to the positions and the offsets of the fingerprint images, and obtaining signals of other pixels in the pixel array by inputting the signals filled in the part of pixels in the pixel array into an artificial intelligence engine. The method further includes generating a candidate fingerprint image and recognizing a user based on the candidate fingerprint image.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: September 13, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Jian-Lung Chen, Chih-Chia Chang, Yu-Hsin Lin, Yu-Ju Chao, Ting-Hsun Cheng
  • Patent number: 11442210
    Abstract: A polarizer substrate includes a substrate, a reflective layer, and a metal pattern layer. The reflective layer is located on the substrate and has a transmission area and a reflective area. The metal pattern layer is located on the reflective layer and the substrate. The metal pattern layer includes a polarizer structure and a microstructure. The polarizer structure includes a plurality of grid lines overlapping the transmission area. A thickness of each of the grid lines is 200 nm to 500 nm, a width of each of the grid lines is 30 nm to 70 nm, and a distance between each adjacent two of the grid lines is 30 nm to 70 nm. The microstructure overlaps the reflective area, and a thickness of the microstructure is 20 nm to 500 nm.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: September 13, 2022
    Assignee: Au Optronics Corporation
    Inventors: Sheng-Kai Lin, Chia-Hsin Chung, Tsai-Sheng Lo, Sheng-Ming Huang, Ming-Jui Wang, Chih-Chiang Chen, Hui-Ku Chang, Cheng-Chan Wang, Chia-Po Lin, Jen-Kuei Lu
  • Publication number: 20220278091
    Abstract: A semiconductor structure including first finfet cells and second finfet cells. Each of the first finfet cells has an analog fin boundary according to analog circuit design rules, and each of the second finfet cells has a digital fin boundary according to digital circuit design rules. The semiconductor structure further includes first circuits formed with the first finfet cells, second circuits formed with the second finfet cells, and third circuits formed with one or more of the first finfet cells and one or more of the second finfet cells.
    Type: Application
    Filed: December 6, 2021
    Publication date: September 1, 2022
    Inventors: Chung-Hui Chen, Weichih Chen, Tien-Chien Huang, Chien-Chun Tsai, Ruey-Bin Sheen, Tsung-Hsin Yu, Chih-Hsien Chang, Cheng-Hsiang Hsieh
  • Patent number: 11422330
    Abstract: A driving mechanism for moving an optical element is provided, including a movable portion, a fixed portion, a driving assembly, and a first resilient element. The movable portion is for connecting the optical element. The movable portion is movable relative to the fixed portion. The driving assembly drives the movable portion to move relative to the fixed portion. The first resilient element has a board structure. The movable portion is movably connected to the fixed portion via the first resilient element. The fixed portion includes a connection surface, a restricting surface, and a recessed portion. At least a portion of the first resilient element is disposed on the connection surface. The restricting surface contacts and restricts the movable portion. The recessed portion is located between the connection surface and the restricting surface, wherein the recessed portion is lower than the connection surface and the restricting surface.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: August 23, 2022
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Bing-Ru Song, Yi-Ho Chen, Chia-Pin Hsu, Chih-Wei Weng, Shin-Hua Chen, Chien-Lun Huang, Chao-Chun Chang, Shou-Jen Liu, Kun-Shih Lin, Nai-Wen Hsu, Yu-Cheng Lin, Shang-Yu Hsu, Yu-Huai Liao, Yi-Hsin Nieh, Shih-Ting Huang, Kuo-Chun Kao, Fu-Yuan Wu
  • Patent number: 11424632
    Abstract: An improved USB charging apparatus includes a main body and a plurality of power processing modules arranged in the main body; each one of the power processing modules having two USB charging ports connected thereto, and the two USB charging ports configured to be a first charging port and a second charging port having specifications different from each other; the first charging port and the second charging port arranged adjacent to each other; each one of the power processing modules further comprising a detection control circuit and a switch circuit, allowing each charging circuit to be provided with the charging ports of two types of specifications, such that user can choose one of the charging ports for use depending upon the actual needs. Accordingly, the improved USB charging apparatus is not limited to certain specifications of charging ports only, thereby increasing the use significantly.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: August 23, 2022
    Assignee: E-SENSE TECHNOLOGY CO., LTD.
    Inventors: Chih Hsin Chen, Shih Che Chiu
  • Publication number: 20220246758
    Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.
    Type: Application
    Filed: April 15, 2022
    Publication date: August 4, 2022
    Applicant: eMemory Technology Inc.
    Inventors: Chih-Hsin Chen, Shih-Chen Wang, Tsung-Mu Lai, Wen-Hao Ching, Chun-Yuan Lo, Wei-Chen Chang
  • Patent number: 11404113
    Abstract: A memory device includes a first program line and a second program line. A first portion of the first program line is formed in a first conductive layer, and a second portion of the first program line is formed in a second conductive layer above the first conductive layer. A first portion of the second program line is formed in the first conductive layer. A second portion of the second program line is formed in the second conductive layer. A third portion of the second program line is formed in a third conductive layer above the second conductive layer. The first portion and the second portion of the first program line have sizes that are different from each other, and the first portion, the second portion and the third portion of the second program line have sizes that are different from each other.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsin Nien, Wei-Chang Zhao, Chih-Yu Lin, Hidehiro Fujiwara, Yen-Huei Chen, Ru-Yu Wang
  • Patent number: 11398259
    Abstract: A memory cell array of a multi-time programmable non-volatile memory includes plural memory cells. The memory cell has the structure of 1T1C cell, 2T1C cell or 3T1C cell. Moreover, the floating gate transistors of the memory cells in different rows of the memory cell array are constructed in the same well region. Consequently, the chip size is reduced. Moreover, by providing proper bias voltages to the memory cell array, the program action, the erase action or the read action can be performed normally.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: July 26, 2022
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chih-Hsin Chen, Chun-Yuan Lo, Shih-Chen Wang, Tsung-Mu Lai
  • Patent number: 11392003
    Abstract: An active device substrate including a substrate, first metal grid wires, a first transparent conductive layer, a gate insulating layer, a semiconductor layer, a source, and a drain is provided. The first metal grid wires are located on the substrate. The first transparent conductive layer includes a scan line and a gate connected to the scan line. The scan line and/or the gate is directly connected to at least a part of the first metal grid wires. The gate insulating layer is located on the first transparent conductive layer. The semiconductor layer is located on the gate insulating layer and overlapped with the gate. The source and the drain are electrically connected to the semiconductor layer.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: July 19, 2022
    Assignee: Au Optronics Corporation
    Inventors: Cheng-Chan Wang, Tsai-Sheng Lo, Chia-Hsin Chung, Chih-Chiang Chen, Hui-Ku Chang, Sheng-Kai Lin, Chia-Po Lin, Ming-Jui Wang, Sheng-Ming Huang, Jen-Kuei Lu
  • Patent number: 11393959
    Abstract: A micro light-emitting diode device includes a substrate, a micro light-emitting diode, a first protection layer and a second protection layer. The micro light-emitting diode is disposed on the substrate. The first protection layer is disposed on a first portion of an outer side wall of the micro light-emitting diode and has a gap from the substrate. The second protection layer is at least disposed on a second portion of the outer side wall and is located in the gap between the first protection layer and the substrate. A height of the second protection layer on the substrate is less than or equal to a height of the micro light-emitting diode on the substrate.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: July 19, 2022
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Pei-Hsin Chen, Yi-Chun Shih, Chih-Ling Wu