Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

Abstract: A memory cell array of a multi-time programmable non-volatile memory includes plural memory cells. The memory cell has the structure of 1T1C cell, 2T1C cell or 3T1C cell. Moreover, the floating gate transistors of the memory cells in different rows of the memory cell array are constructed in the same well region. Consequently, the chip size is reduced. Moreover, by providing proper bias voltages to the memory cell array, the program action, the erase action or the read action can be performed normally.

Abstract: The invention is a UV sterilizing box structure. A box body has a round chamber, an inlet, and an outlet. The round chamber is formed with an arc-shaped guiding channel. A UV light module is disposed on a side of the box body. An external fluid enters the round chamber via the inlet and spirally flows through an inside of the round chamber along the arc-shaped guiding channel so as to make the fluid in the box body generate a flow with a specific direction and stay for enough time to be sufficiently irradiated by UV rays. Thereby, a better effect of sterilization may be obtained.

Abstract: The invention is a UV sterilizing box structure. A box body has a round chamber, an inlet, and an outlet. The round chamber is formed with an arc-shaped guiding channel. A UV light module is disposed on a side of the box body. An external fluid enters the round chamber via the inlet and spirally flows through an inside of the round chamber along the arc-shaped guiding channel so as to make the fluid in the box body generate a flow with a specific direction and stay for enough time to be sufficiently irradiated by UV rays. Thereby, a better effect of sterilization may be obtained.

Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

Abstract: An improved USB charging apparatus includes a main body and a plurality of power processing modules arranged in the main body; each one of the power processing modules having two USB charging ports connected thereto, and the two USB charging ports configured to be a first charging port and a second charging port having specifications different from each other; the first charging port and the second charging port arranged adjacent to each other; each one of the power processing modules further comprising a detection control circuit and a switch circuit, allowing each charging circuit to be provided with the charging ports of two types of specifications, such that user can choose one of the charging ports for use depending upon the actual needs. Accordingly, the improved USB charging apparatus is not limited to certain specifications of charging ports only, thereby increasing the use significantly.

Abstract: The present invention provides a circuitry of a biopotential acquisition system comprising an input node, an ETI transmitter and an ADC. The input node is coupled to an electrode of the biopotential acquisition system, and the electrode is used to be in contact with a human body. The ETI transmitter is configured to generate a transmitter signal to the input node. The ADC is coupled to the input node, and is configured to process an input signal from the input node to generate a digital signal, wherein each of the input signal and the digital signal comprises components of an ECG signal and an ETI signal.

Abstract: A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region. The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.

Abstract: The present invention provides a circuitry of a biopotential acquisition system, where the circuitry includes an input node, an ETI transmitter, a capacitor and an ETI receiver. The input node is configured to receive an input signal from an electrode of the biopotential acquisition system. The ETI transmitter is configured to generate a transmitter signal. A first node of the capacitor is coupled to the ETI transmitter, and a second node of the capacitor is coupled to the input node. The ETI receiver is coupled to the input node, and is configured to receive the transmitter signal via the capacitor to generate an ETI.

Abstract: A memory cell array of a multi-time programmable non-volatile memory includes plural memory cells. The memory cell has the structure of 1T1C cell, 2T1C cell or 3T1C cell. Moreover, the floating gate transistors of the memory cells in different rows of the memory cell array are constructed in the same well region. Consequently, the chip size is reduced. Moreover, by providing proper bias voltages to the memory cell array, the program action, the erase action or the read action can be performed normally.

Abstract: The present invention provides a lead-on detection circuitry of a biopotential acquisition system. The lead-on detection circuitry includes an input terminal, a duty-cycle controller, a transmitting signal generator and a mixer-based receiver. The duty-cycle controller is configured to generate a first clock signal. The transmitting signal generator is configured to generate a transmitting signal to the input terminal according to the first clock signal. The mixer-based receiver is configured to perform a mixing operation based on the first clock signal and the transmitting signal to generate an output signal, wherein the output signal indicates if an electrode of the biopotential acquisition system is in contact with a human body, and the electrode is coupled to the input terminal.

Abstract: A near-memory computation system includes a plurality of computation nodes. Each computation node receives a plurality of input signals and outputs a computing result signal. The computation node includes a plurality of non-volatile memory cells and a processing element. Each non-volatile memory cell stores a weighting value during a program operation and outputs a weighting signal according to the weighting value during a read operation. The processing element is coupled to the plurality of non-volatile memory cells. The processing element receives the plurality of input signals and generates the computing result signal by performing computations with the plurality of input signals and a plurality of weighting signals generated by the plurality of non-volatile memory cells. The plurality of non-volatile memory cells and the processing element are manufactured by different or the same processes.

Abstract: A multi-cell per bit nonvolatile memory (NVM) unit includes a select transistor disposed on a first oxide define (OD) region, a word line transistor disposed on the first OD region, and serially connected floating gate transistors disposed between the select transistor and the word line transistor. A first floating gate extension continuously extends toward a second OD region and adjacent to an erase gate region. A second floating gate extension continuously extends toward a third OD region and is capacitively coupled to a control gate region. A channel length of each of the floating gate transistors is shorter than that of the select transistor or the word line transistor.

Abstract: A multi-time programming memory cell includes a floating gate transistor, a first capacitor, a second capacitor and a third capacitor. The floating gate transistor has a floating gate. A first terminal of the floating gate transistor is coupled to a source line. A second terminal of the floating gate transistor is coupled to a bit line. A first terminal of the first capacitor is connected with the floating gate. A second terminal of the first capacitor is connected with an erase line. A first terminal of the second capacitor is connected with the floating gate. A second terminal of the second capacitor is connected with a control line. A first terminal of the third capacitor is connected with the floating gate. A second terminal of the third capacitor is connected with an inhibit line.

Abstract: A non-volatile memory cell includes a storage transistor having a first terminal, a second terminal, and a gate terminal. During a program operation, the first terminal of the storage transistor receives a data voltage according to a weighting to be stored in the non-volatile memory cell, the second terminal of the storage transistor is floating, and the gate terminal of the storage transistor is coupled to a program voltage. The program voltage is greater than the data voltage.

Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

Abstract: A random bit cell includes a latch and a nonvolatile memory cell. The nonvolatile memory cell includes a storage circuit, a control element, an erase element, and a read circuit. The storage circuit is coupled to a first terminal of the latch. The storage circuit includes a floating gate transistor having a first terminal, a second terminal, and a floating gate. The control element has a first terminal coupled to a control line, and a control terminal coupled to the floating gate of the floating gate transistor. The erase element has a first terminal coupled to an erase line, and a control terminal coupled to the floating gate of the floating gate transistor. The read circuit is coupled to a bit line, a select gate line, and the floating gate of the floating gate transistor.

Abstract: A near-memory computation system includes a plurality of computation nodes. Each computation node receives a plurality of input signals and outputs a computing result signal. The computation node includes a plurality of non-volatile memory cells and a processing element. Each non-volatile memory cell stores a weighting value during a program operation and outputs a weighting signal according to the weighting value during a read operation. The processing element is coupled to the plurality of non-volatile memory cells. The processing element receives the plurality of input signals and generates the computing result signal by perform computations with the plurality of input signals and a plurality of weighting signals generated by the plurality of non-volatile memory cells. The plurality of non-volatile memory cells and the processing element are manufactured by different or the same processes.

Abstract: A random bit cell includes a latch and a nonvolatile memory cell. The nonvolatile memory cell includes a storage circuit, a control element, an erase element, and a read circuit. The storage circuit is coupled to a first terminal of the latch. The storage circuit includes a floating gate transistor having a first terminal, a second terminal, and a floating gate. The control element has a first terminal coupled to a control line, and a control terminal coupled to the floating gate of the floating gate transistor. The erase element has a first terminal coupled to an erase line, and a control terminal coupled to the floating gate of the floating gate transistor. The read circuit is coupled to a bit line, a select gate line, and the floating gate of the floating gate transistor.

Abstract: A liquid crystal composition includes a nematic liquid crystal, and a compound of Formula (I) where R is an alkyl, aryl, aralkyl or heteroaryl having 6 to 30 carbon atoms, wherein the compound accounts for 0.3 to 0.6% of the liquid crystal composition. Further, a sensing device includes a substrate, a frame, an alignment film, the liquid crystal composition as described above, and two polarizers. The frame is connected to the substrate and forms an accommodation space having an opening, and the alignment film and the liquid crystal composition are both located inside the accommodation space. One of the polarizers is arranged in correspondence with the opening such that a channel exists between the polarizer and the frame, the other polarizer is located at a lateral side of the substrate, and the polarization directions of the two polarizers intersect with each other.