Patents by Inventor Chih-Hsin Chen
Chih-Hsin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200202941Abstract: A non-volatile memory cell includes a storage transistor having a first terminal, a second terminal, and a gate terminal. During a program operation, the first terminal of the storage transistor receives a data voltage according to a weighting to be stored in the non-volatile memory cell, the second terminal of the storage transistor is floating, and the gate terminal of the storage transistor is coupled to a program voltage. The program voltage is greater than the data voltage.Type: ApplicationFiled: October 30, 2019Publication date: June 25, 2020Inventors: Tsung-Mu Lai, Chih-Hsin Chen, Chun-Fu Lin
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Publication number: 20200194079Abstract: A multi-time programming memory cell includes a floating gate transistor, a first capacitor, a second capacitor and a third capacitor. The floating gate transistor has a floating gate. A first terminal of the floating gate transistor is coupled to a source line. A second terminal of the floating gate transistor is coupled to a bit line. A first terminal of the first capacitor is connected with the floating gate. A second terminal of the first capacitor is connected with an erase line. A first terminal of the second capacitor is connected with the floating gate. A second terminal of the second capacitor is connected with a control line. A first terminal of the third capacitor is connected with the floating gate. A second terminal of the third capacitor is connected with an inhibit line.Type: ApplicationFiled: October 23, 2019Publication date: June 18, 2020Inventor: Chih-Hsin Chen
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Publication number: 20200163574Abstract: The present invention provides a circuit applied to a biopotential acquisition system, wherein the circuit includes an active current source and an amplifier. In the operations of the circuit, the active current source is configured to provide a current to two input terminals of the circuit, wherein the two input terminals of the circuit are coupled to two input electrodes of the biopotential acquisition system; and the amplifier is configured to receive input signals from the two input terminals to generate an output signal.Type: ApplicationFiled: November 12, 2019Publication date: May 28, 2020Inventor: Chih-Hsin Chen
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Publication number: 20200163577Abstract: The present invention provides a circuit applied to a bio-information acquisition system, wherein the circuit includes a terminal, an output circuit, a feedback circuit and a calibration circuit. In the operations of the circuit, the terminal is arranged to receive an input signal, the output circuit is configured to generate an output signal according to the input signal, the feedback circuit is configured to receive the output signal to generate a current signal to the terminal, and the calibration circuit is configured to generate a control signal to control the feedback circuit to determine a level of the current signal according to the output signal.Type: ApplicationFiled: November 12, 2019Publication date: May 28, 2020Inventors: Chih-Hsin Chen, Yu-Hung Lin
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Patent number: 10642579Abstract: A non-volatile memory includes a memory cell. A storage element of the memory cell has following structures. A first floating gate transistor includes a first floating gate, a first source/drain terminal and a second source/drain terminal. A second floating gate transistor includes the first floating gate, a third source/drain terminal and a fourth source/drain terminal. A third floating gate transistor includes a second floating gate, a fifth source/drain terminal and a sixth source/drain terminal. A fourth floating gate transistor includes the second floating gate, a seventh source/drain terminal and an eighth source/drain terminal. The first and third source/drain terminals are connected with a first terminal of the storage element. The second and fifth source/drain terminals are connected with each other. The fourth and seventh source/drain terminals are connected with each other. The sixth and eighth source/drain terminals are connected with a second terminal of the storage element.Type: GrantFiled: May 25, 2018Date of Patent: May 5, 2020Assignee: EMEMORY TECHNOLOGY INC.Inventors: Chih-Hsin Chen, Shih-Chen Wang
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Publication number: 20200079915Abstract: The invention relates to a method for preparing a polymer gel film containing liquid crystal droplets, comprising the steps of: preparing liquid crystal droplets containing a ligand, by adding a nematic liquid crystal containing a ligand to an aqueous surfactant solution, and mixing, to obtain the liquid crystal droplets containing a ligand; adding the liquid crystal droplets containing a ligand to an aqueous polymer solution, and mixing, to obtain an aqueous polymer solution containing the liquid crystal droplets; and spreading the aqueous polymer solution containing the liquid crystal droplets flatly in a polymer container, and allowing the aqueous polymer solution containing the liquid crystal droplets to gelatinize, to obtain a polymer gel film containing liquid crystal droplets. The invention utilizes liquid crystal droplets dispersed in the agarose to detect mercuric ions in the water, and through the configuration change of the liquid crystal droplets, the mercuric ions is specifically detected.Type: ApplicationFiled: July 11, 2019Publication date: March 12, 2020Inventors: CHIH-HSIN CHEN, JHIH-WEI HUANG, JUNG-JUNG CHANG
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Publication number: 20200025749Abstract: A detection device includes a rectangular tube, an alignment film, a probe, and a nematic liquid crystal (LC). The rectangular tube has a tube wall and a receiving space located inside the tube wall. The tube wall has one or more light-transmittable region. The alignment film is located on the tube wall and corresponds to the light-transmittable region. The probe is distributed on the alignment film. The nematic LC is located in the receiving space. The probe includes an antibody, an antigen, or both the antibody and the antigen. Furthermore, a detection system is also provided.Type: ApplicationFiled: May 28, 2019Publication date: January 23, 2020Applicant: Tamkang UniversityInventors: Chih-Hsin Chen, Jhih-Wei Huang
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Publication number: 20200006508Abstract: A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region. The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.Type: ApplicationFiled: March 29, 2019Publication date: January 2, 2020Inventors: Chun-Yuan LO, Shih-Chen WANG, Wen-Hao CHING, Chih-Hsin CHEN, Wei-Ren CHEN
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Publication number: 20190164981Abstract: A multi-cell per bit nonvolatile memory (NVM) unit includes a select transistor disposed on a first oxide define (OD) region, a word line transistor disposed on the first OD region, and serially connected floating gate transistors disposed between the select transistor and the word line transistor. A first floating gate extension continuously extends toward a second OD region and adjacent to an erase gate region. A second floating gate extension continuously extends toward a third OD region and is capacitively coupled to a control gate region. A channel length of each of the floating gate transistors is shorter than that of the select transistor or the word line transistor.Type: ApplicationFiled: June 6, 2018Publication date: May 30, 2019Inventors: Chih-Hsin Chen, Tsung-Mu Lai, Shih-Chen Wang
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Publication number: 20190115076Abstract: A non-volatile memory includes a memory cell. A storage element of the memory cell has following structures. A first floating gate transistor includes a first floating gate, a first source/drain terminal and a second source/drain terminal. A second floating gate transistor includes the first floating gate, a third source/drain terminal and a fourth source/drain terminal. A third floating gate transistor includes a second floating gate, a fifth source/drain terminal and a sixth source/drain terminal. A fourth floating gate transistor includes the second floating gate, a seventh source/drain terminal and an eighth source/drain terminal. The first and third source/drain terminals are connected with a first terminal of the storage element. The second and fifth source/drain terminals are connected with each other. The fourth and seventh source/drain terminals are connected with each other. The sixth and eighth source/drain terminals are connected with a second terminal of the storage element.Type: ApplicationFiled: May 25, 2018Publication date: April 18, 2019Inventors: Chih-Hsin CHEN, Shih-Chen Wang
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Publication number: 20180156764Abstract: A liquid crystal composition includes a nematic liquid crystal, and a compound of Formula (I) where R is an alkyl, aryl, aralkyl or heteroaryl having 6 to 30 carbon atoms, wherein the compound accounts for 0.3 to 0.6% of the liquid crystal composition. Further, a sensing device includes a substrate, a frame, an alignment film, the liquid crystal composition as described above, and two polarizers. The frame is connected to the substrate and forms an accommodation space having an opening, and the alignment film and the liquid crystal composition are both located inside the accommodation space. One of the polarizers is arranged in correspondence with the opening such that a channel exists between the polarizer and the frame, the other polarizer is located at a lateral side of the substrate, and the polarization directions of the two polarizers intersect with each other.Type: ApplicationFiled: July 7, 2017Publication date: June 7, 2018Inventors: Chih-Hsin Chen, Wei-Long Chen, Tsung-Yang Ho
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Patent number: 9847133Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory bytes, each memory byte includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. Memory bytes of the same column are coupled to the same erase line, and memory bytes of different columns are coupled to different erase lines. Therefore, the memory array is able to support byte operations while the memory cells of the same memory byte can share the same wells. The circuit area of the memory array can be reduced and the operation of the memory array can be more flexible.Type: GrantFiled: May 10, 2016Date of Patent: December 19, 2017Assignee: eMemory Technology Inc.Inventors: Tsung-Mu Lai, Chih-Hsin Chen, Shih-Chen Wang, Chen-Hao Po
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Publication number: 20170206970Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory bytes, each memory byte includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. Memory bytes of the same column are coupled to the same erase line, and memory bytes of different columns are coupled to different erase lines. Therefore, the memory array is able to support byte operations while the memory cells of the same memory byte can share the same wells. The circuit area of the memory array can be reduced and the operation of the memory array can be more flexible.Type: ApplicationFiled: May 10, 2016Publication date: July 20, 2017Inventors: Tsung-Mu Lai, Chih-Hsin Chen, Shih-Chen Wang, Chen-Hao Po
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Patent number: 9524785Abstract: A memory cell includes a floating gate transistor, a word line transistor, a first capacitance element, and a second capacitance element. The floating gate transistor has a first terminal for receiving a bit line signal, a second terminal, and a floating gate. The word line transistor has a first terminal coupled to the second terminal of the floating gate transistor, a second terminal for receiving a third voltage, and a control terminal for receiving a word line signal. A voltage passing device is for outputting a second voltage during an inhibit operation and a first voltage during a program operation or an erase operation. The first capacitance element is coupled to the first voltage passing device and the floating gate, and for receiving a first control signal. The second capacitance element is for receiving at a second control signal.Type: GrantFiled: March 10, 2016Date of Patent: December 20, 2016Assignee: eMemory Technology Inc.Inventors: Chih-Hsin Chen, Shih-Chen Wang, Tsung-Mu Lai
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Patent number: 9466392Abstract: A memory array includes a first memory page and a second memory page. The first memory page includes a first word line, a first select gate line, a first control line, a first erase line, and a plurality of first memory cells each coupled to the first word line, the first select gate line, the first control line, and the first erase line, and for receiving a bit line signal and a source line signal. The second memory page includes a second control line, a second erase line, and a plurality of second memory cells each coupled to the first word line, the first select gate line, the second control line, and the second erase line, and for receiving a bit line signal and a source line signal.Type: GrantFiled: October 13, 2015Date of Patent: October 11, 2016Assignee: eMemory Technology Inc.Inventors: Wei-Chen Chang, Wen-Hao Ching, Chih-Hsin Chen, Shih-Chen Wang, Ching-Sung Yang
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Publication number: 20160293261Abstract: A memory cell includes a floating gate transistor, a word line transistor, a first capacitance element, and a second capacitance element. The floating gate transistor has a first terminal for receiving a bit line signal, a second terminal, and a floating gate. The word line transistor has a first terminal coupled to the second terminal of the floating gate transistor, a second terminal for receiving a third voltage, and a control terminal for receiving a word line signal. A voltage passing device is for outputting a second voltage during an inhibit operation and a first voltage during a program operation or an erase operation. The first capacitance element is coupled to the first voltage passing device and the floating gate, and for receiving a first control signal. The second capacitance element is for receiving at a second control signal.Type: ApplicationFiled: March 10, 2016Publication date: October 6, 2016Inventors: Chih-Hsin Chen, Shih-Chen Wang, Tsung-Mu Lai
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Publication number: 20160104537Abstract: A memory array includes a first memory page and a second memory page. The first memory page includes a first word line, a first select gate line, a first control line, a first erase line, and a plurality of first memory cells each coupled to the first word line, the first select gate line, the first control line, and the first erase line, and for receiving a bit line signal and a source line signal. The second memory page includes a second control line, a second erase line, and a plurality of second memory cells each coupled to the first word line, the first select gate line, the second control line, and the second erase line, and for receiving a bit line signal and a source line signal.Type: ApplicationFiled: October 13, 2015Publication date: April 14, 2016Inventors: Wei-Chen Chang, Wen-Hao Ching, Chih-Hsin Chen, Shih-Chen Wang, Ching-Sung Yang
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Patent number: 9041089Abstract: A nonvolatile memory structure includes a substrate having thereon a first, a second, and a third OD regions arranged in a row. The first, second, and third OD regions are separated from one another by an isolation region. The isolation region includes a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second the third OD region. A first select transistor is formed on the first OD region. A floating gate transistor is formed on the second OD region. The floating gate transistor is serially coupled to the first select transistor. The floating gate transistor includes a floating gate completely overlapped with the second OD region and is partially overlapped with the first and second intervening isolation regions. A second select transistor is on the third OD region and serially coupled to the floating gate transistor.Type: GrantFiled: December 27, 2013Date of Patent: May 26, 2015Assignee: eMemory Technology Inc.Inventors: Chih-Hsin Chen, Wei-Ren Chen, Tsung-Mu Lai
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Patent number: 9018691Abstract: A nonvolatile memory structure includes a semiconductor substrate having thereon a first oxide define (OD) region, a second OD region and a third OD region arranged in a row. The first, second, and third OD regions are separated from one another by an isolation region. The isolation region includes a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second OD region and the third OD region. A select gate transistor is formed on the first OD region. A floating gate transistor is formed on the second OD region. The floating gate transistor is serially coupled to the select gate transistor. The floating gate transistor includes a floating gate that is completely overlapped with the underlying second OD region and is partially overlapped with the first and second intervening isolation regions.Type: GrantFiled: July 17, 2013Date of Patent: April 28, 2015Assignee: eMemory Technology Inc.Inventors: Wei-Ren Chen, Te-Hsun Hsu, Chih-Hsin Chen
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Publication number: 20140361358Abstract: A nonvolatile memory structure includes a substrate having thereon a first, a second, and a third OD regions arranged in a row. The first, second, and third OD regions are separated from one another by an isolation region. The isolation region includes a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second the third OD region. A first select transistor is formed on the first OD region. A floating gate transistor is formed on the second OD region. The floating gate transistor is serially coupled to the first select transistor. The floating gate transistor includes a floating gate completely overlapped with the second OD region and is partially overlapped with the first and second intervening isolation regions. A second select transistor is on the third OD region and serially coupled to the floating gate transistor.Type: ApplicationFiled: December 27, 2013Publication date: December 11, 2014Applicant: eMemory Technology Inc.Inventors: Chih-Hsin Chen, Wei-Ren Chen, Tsung-Mu Lai