Abstract: An oscillator wafer-level-package structure is provided, comprising a bottom layer, an oscillator crystal and a capping layer. The bottom layer includes an upper plane, the capping layer includes a lower plane, and the oscillator crystal is disposed between the bottom layer and the capping layer and includes at least one cavity. An upper seal ring and a lower seal ring are respectively surrounding the oscillator crystal such that the oscillator crystal is sealed in between the capping layer and the bottom layer by employing the upper and lower seal rings. In addition, a diffusion barrier is further disposed in the upper seal ring and in the lower seal ring for avoiding interface diffusion. Moreover, the present invention adopts the same material for fabricating the capping layer, the oscillator crystal and the bottom layer to achieve an optimal thermal stress result when realizing the packaging structure.

Abstract: A crystal oscillator and a method for fabricating the same is provided. In the method, a crystal package is provided. The crystal package includes a crystal blank and at least one laser-penetrating area. The laser-penetrating area is exposed outside. The crystal package is provided with at least one airtight space therein. At least one getter is formed in the airtight space. The location of the laser-penetrating area corresponds to that of the getter. A laser beam penetrates through the laser-penetrating area to activate the getter, thereby increasing the degree of vacuum of the airtight space.

Abstract: An oscillator wafer-level-package structure is provided, comprising a bottom layer, an oscillator crystal and a capping layer. The bottom layer includes an upper plane, the capping layer includes a lower plane, and the oscillator crystal is disposed between the bottom layer and the capping layer and includes at least one cavity. An upper seal ring and a lower seal ring are respectively surrounding the oscillator crystal such that the oscillator crystal is sealed in between the capping layer and the bottom layer by employing the upper and lower seal rings. In addition, a diffusion barrier is further disposed in the upper seal ring and in the lower seal ring for avoiding interface diffusion. Moreover, the present invention adopts the same material for fabricating the capping layer, the oscillator crystal and the bottom layer to achieve an optimal thermal stress result when realizing the packaging structure.

Abstract: A TEM specimen kit is disclosed, which comprises: (a) a top substrate and a bottom substrate, the top and the bottom substrates being transparent and substantially parallel to each other; (b) a first spacer and a second spacer, located beneath the top substrate and sitting on the bottom substrate, the second spacer being opposite to and spaced apart from the first spacer at a distance of d; and (c) a chamber formed between the top and bottom substrate and between the first and second spacer, the chamber having two ends open to the atmosphere and characterized by having a height defined by the thickness h of the spacer, wherein the height being smaller than the diameter of a red blood cell. Also enclosed are methods for preparing a dry specimen for TEM nanoparticle characterization, and methods for analyzing TEM images of nanoparticles in a liquid sample.

Abstract: A TEM specimen kit is disclosed, which comprises: (a) a top substrate and a bottom substrate, the top and the bottom substrates being transparent and substantially parallel to each other; (b) a first spacer and a second spacer, located beneath the top substrate and sitting on the bottom substrate, the second spacer being opposite to and spaced apart from the first spacer at a distance of d; and (c) a chamber formed between the top and bottom substrate and between the first and second spacer, the chamber having two ends open to the atmosphere and characterized by having a height defined by the thickness h of the spacer, wherein the height being smaller than the diameter of a red blood cell. Also enclosed are methods for preparing a dry specimen for TEM nanoparticle characterization, and methods for analyzing TEM images of nanoparticles in a liquid sample.

Abstract: A specimen kit having a tiny chamber is disclosed for a specimen preparation for TEM. The space height of the chamber is far smaller than dimensions of blood cells and therefore is adapted to sort nanoparticles from the blood cells. The specimen prepared under this invention is suitable for TEM observation over a true distribution status of nanoparticles in blood. The extremely tiny space height in Z direction eliminates the possibility of aggregation of the nanoparticles and/or agglomeration in Z direction during drying; therefore, a specimen prepared under this invention is suitable for TEM observation over the dispersion and/or agglomeration of nanoparticles in a blood.

Abstract: A specimen kit having a tiny chamber is disclosed for a specimen preparation for TEM. The space height of the chamber is far smaller than dimensions of blood cells and therefore is adapted to sort nanoparticles from the blood cells. The specimen prepared under this invention is suitable for TEM observation over a true distribution status of nanoparticles in blood. The extremely tiny space height in Z direction eliminates the possibility of aggregation of the nanoparticles and/or agglomeration in Z direction during drying; therefore, a specimen prepared under this invention is suitable for TEM observation over the dispersion and/or agglomeration of nanoparticles in a blood.

Abstract: A method of fabricating a recess channel transistor is provided. First, a hard mask is formed on a doped-semiconductor layer and a substrate. The doped-semiconductor layer and the substrate are etched to form a trench and define a source/drain in the doped-semiconductor layer. An implantation process is performed with a tilt angle on sidewalls of the trench to form an implant area. A thermal oxidation process is performed to form an oxide layer. The oxide layer comprises a first thickness on the source/drain in the sidewalls of the trench and a second thickness on the other portion in the sidewalls of the trench.

Abstract: A solar cell includes a semiconductor substrate, an emitter layer, at least one emitter contact region and at least one first electrode. The emitter layer is formed on at least one surface of the semiconductor substrate. A p-n junction is formed between the emitter layer and the semiconductor substrate. The emitter contact region is formed on portions of the emitter layer and has the same type of dopant as the emitter layer. The emitter contact region has a higher dopant concentration than the emitter layer. The first electrode is coupled with the emitter contact region.

Abstract: A photovoltaic power device is provided. The photovoltaic power device includes a donor substrate, a first emitting substrate; a second emitting substrate, a first anti-reflection layer, a first metal electrode, a second metal electrode and a second anti-reflection layer. In the photovoltaic power device, the first and the second emitting substrate are disposed in the opposite sides of the donor substrate to generate two electronic flows, and the first metal electrode is insulated from the second metal electrode by the second anti-reflection layer.

Abstract: A semiconductor device is provided. The semiconductor device has a gate structure, a source region, a drain region, and a pair of dielectric barrier layers. The gate structure is formed on a substrate. The source region and the drain region are formed in the substrate next to the gate structure, and a channel region is formed between the source region and the drain region underneath the gate structure. The pair of dielectric barrier layers is respectively formed in the substrate underneath the gate structure between the source region and the drain region. The dielectric barrier layers are used for reducing the drain induced barrier lowering effect in a nanometer scale device.

Abstract: A reduced area dynamic random access memory (DRAM) cell and method for fabricating the same wherein the cell occupies an area smaller than one photolithography pitch by two photolithography pitches through the formation of sidewall spacers along a first pattern to define a first portion of the active region of the memory cell and a second orthogonally oriented pattern to define a second portion of the active region of the memory cell thereby creating a ladder shaped active region for a column of the memory cells.

Abstract: A method of fabricating a recess channel transistor is provided. First, a hard mask is formed on a doped-semiconductor layer and a substrate. The doped-semiconductor layer and the substrate are etched to form a trench and define a source/drain in the doped-semiconductor layer. An implantation process is performed with a tilt angle on sidewalls of the trench to form an implant area. A thermal oxidation process is performed to form an oxide layer. The oxide layer comprises a first thickness on the source/drain in the sidewalls of the trench and a second thickness on the other portion in the sidewalls of the trench.

Abstract: A method for manufacturing a non-volatile memory is provided. First, a tunneling dielectric layer is formed over a substrate. A plurality of silicon nanocrystals is formed on the tunneling dielectric layer. A silicide process is performed on the silicon nanocrystals to form a plurality of salicide nanocrystals. A dielectric layer and a conductive layer are sequentially formed on the substrate to cover the salicide nanocrystals and the tunneling dielectric layer. The conductive layer, the dielectric layer, the salicide nanocrystals and the tunneling dielectric layer are patterned to form a gate structure. A source/drain region is formed in the substrate on the respective sides of the gate structure.

Abstract: A reduced area dynamic random access memory (DRAM) cell and method for fabricating the same wherein the cell occupies an area smaller than one photolithography pitch by two photolithography pitches through the formation of sidewall spacers along a first pattern to define a first portion of the active region of the memory cell and a second orthogonally oriented pattern to define a second portion of the active region of the memory cell thereby creating a ladder shaped active region for a column of the memory cells.

Abstract: A semiconductor device is provided. The semiconductor device has a gate structure, a source region, a drain region, and a pair of dielectric barrier layers. The gate structure is formed on a substrate. The source region and the drain region are formed in the substrate next to the gate structure, and a channel region is formed between the source region and the drain region underneath the gate structure. The pair of dielectric barrier layers is respectively formed in the substrate underneath the gate structure between the source region and the drain region. The dielectric barrier layers are used for reducing the drain induced barrier lowering effect in a nanometer scale device.

Abstract: A method for writing a memory module includes providing a plurality of memory cells, applying a first transmission line voltage to the first transmission line of the column of a memory cell, turning on a P-type channel of a memory cell between the memory cell to be written and the first transmission line of the column of the memory cell, turning off the P-type channel of at least one memory cell between the memory cell and the second transmission line of the column of the memory cell, applying a word line voltage to a word line connected to the memory cell, in order to inject hot electrons on a junction between the substrate and the first P-type doped region of the memory cell into a silicon nitride layer of the memory cell using band-to-band tunneling injection, and applying a substrate voltage to the substrates of the plurality of memory cells.

Abstract: A system on chip (SOC) contains a core circuit and an input/output (I/O) circuit embedded with an array of single-poly erasable programmable read only memory cells, each of which comprises a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P-type substrate. The first PMOS transistor includes a single-poly floating gate, a first P+ doped drain region and a first P+ doped source region, the second PMOS transistor includes a single-poly select gate and a second P+ doped source region, and the first P+ doped source region of the first PMOS transistor serves as a drain of the second PMOS transistor.

Abstract: A method for writing a memory module includes providing a plurality of memory cells, applying a first transmission line voltage to the first transmission line of the column of a memory cell, turning on a P-type channel of a memory cell between the memory cell to be written and the first transmission line of the column of the memory cell, turning off the P-type channel of at least one memory cell between the memory cell and the second transmission line of the column of the memory cell, applying a word line voltage to a word line connected to the memory cell, in order to inject hot electrons on a junction between the substrate and the first P-type doped region of the memory cell into a silicon nitride layer of the memory cell using band-to-band tunneling injection, and applying a substrate voltage to the substrates of the plurality of memory cells.

Abstract: A method for programming PMOS single transistor flash memory cells through channel hot carrier induced hot electron injection mechanism is disclosed. The PMOS single transistor flash memory cell includes an ONO stack layer situated on an N-well of a semiconductor substrate, a P+ poly gate formed on the ONO stack layer, a P+ doped source region disposed in the N-well at one side of the gate, and a P+ doped drain region disposed in the N-well at the other side of the gate. The method includes the steps of: applying a word line voltage VWL on the P+ poly gate, applying a source line voltage VSL on the source, wherein the source line voltage VSL is greater than the word line voltage VWL, thereby providing adequate bias to turn on the P channel thereof.