Abstract: A wafer has a substrate defined with a first region and a second region. An ONO layer, a first silicon layer, and a silicon nitride layer are formed on the substrate in sequence. Then the ONO layer, the first silicon layer, and the silicon nitride layer disposed on the second region are removed. At least one gate oxide layer is formed on the second region and a second silicon layer is deposited on the wafer. After that, a photo-etching process is performed to remove the second silicon layer and the silicon nitride layer on the first region. At least a third silicon layer is formed on the wafer. Photo-etching processes and a plurality of ion implantation processes are then performed to form a gate, a drain, and a source of each MOS transistor on the substrate.

Abstract: A wafer has a substrate defined with a first region and a second region. An ONO layer, a first silicon layer, and a silicon nitride layer are formed on the substrate in sequence. Then the ONO layer, the first silicon layer, and the silicon nitride layer disposed on the second region are removed. At least one gate oxide layer is formed on the second region and a second silicon layer is deposited on the wafer. After that, a photo-etching process is performed to remove the second silicon layer and the silicon nitride layer on the first region. At least a third silicon layer is formed on the wafer. Photo-etching processes and a plurality of ion implantation processes are then performed to form a gate, a drain, and a source of each MOS transistor on the substrate.

Abstract: A system on chip (SOC) contains a core circuit and an input/output (I/O) circuit embedded with an array of single-poly erasable programmable read only memory cells, each of which comprises a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P-type substrate. The first PMOS transistor includes a single-poly floating gate, a first P+ doped drain region and a first P+ doped source region, the second PMOS transistor includes a single-poly select gate and a second P+ doped source region, and the first P+ doped source region of the first PMOS transistor serves as a drain of the second PMOS transistor.

Abstract: A method for forming an electrically programmable read-only memory(EPROM) includes forming a first p+ doped region, a second p+ doped region, and a third p+ doped region on an N-well, forming a control gate between the first p+ doped region and the second p+ doped region, and forming a p+ floating gate between the second p+ doped region and the third p+ doped region.

Abstract: An electrically erasable programmable logic device (EEPLD) includes a P type semiconductor substrate. An N type well is formed on the P type semiconductor substrate. A first PMOS transistor is formed on the N well. The first PMOS transistor comprises a floating gate, a first P+ doped region serving as a drain of the first PMOS transistor, and a P− doped region encompassing an N+ doped region for erasing the first PMOS transistor. A second PMOS transistor is also formed on the N well and serially connected to the first PMOS transistor. The first P+ doped region functions as a source of the second PMOS transistor, and the second PMOS transistor further comprises a select gate and a second P+ doped region serving as a drain of the second PMOS transistor.

Abstract: A method for manufacturing the lower electrode of a DRAM capacitor. The method includes depositing polysilicon instead of amorphous silicon to form the lower electrode. Because polysilicon has a higher depositing temperature, it has a higher depositing rate capable of shortening depositing time. After forming the polysilicon lower electrode, the upper portion of the polysilicon layer is transformed into an amorphous layer by bombarding the polysilicon layer with ions to damage its internal structure. Eventually, hemispherical grain silicon is able to grow over the lower electrode, thereby increasing its surface area.

Abstract: A method for fabricating an embedded dynamic random access memory (DRAM) is provided. The method contains implanting ions onto the substrate at a DRAM active area and a logic circuit with different dopant concentration. A thermal oxidation process is performed to form a DRAM gate oxide layer with a greater thickness than that of a logic gate oxide layer. A DRAM MOS transistor is formed at a DRAM region and a logic MOS transistor is formed at a logic region. The DRAM MOS transistor has a polycide gate structure. The logic transistor has a first self-aligned silicide (Salicide) layer on its gate structure, and a second Salicide on its interchangeable source/drain region. A dielectric layer is formed over the substrate. A contact opening is formed in the dielectric layer by patterning the dielectric layer to expose the interchangeable source/drain region of the DRAM transistor. A stack capacitor is formed on the dielectric layer.

Abstract: A method for recovering the alignment mark on a substrate to the top of a dielectric layer. The method includes the steps of forming a dielectric layer over a substrate, and then forming a cap layer over the dielectric layer. The cap layer fills the trench in the dielectric layer directly above the alignment mark and covers the area surrounding the trench. Thereafter, a global planarization is carried out to remove the top portion of the cap layer. Finally, the remaining portion of the cap layer is removed to expose the dielectric layer so that an alignment mark re-emerges on top of the dielectric layer.

Abstract: The invention provides a method of forming shallow trench isolation. In the method, a first mask and a second mask layer are made of polysilicon and silicon oxide, respectively. Part of the first mask layer is oxidized into a protective oxide layer during thermal oxidation for forming a liner oxide layer. The protective oxide layer can protect the top corner of a trench from he formation of pits during subsequent etching for removing a pad oxide layer, thereby preventing a kink effect. Furthermore, after forming the liner oxide layer and before filling the trench with an insulting layer, a buffer layer formed over a substrate not only prevents the sidewalls of the trench from oxidizing, but also prevents a lateral etching damage during subsequent etching for removing the pad oxide layer.

Abstract: A method for recovering the alignment mark on a substrate to the top of a dielectric layer. The method includes the steps of forming a dielectric layer over a substrate, and then forming a cap layer over the dielectric layer. The cap layer fills the trench in the dielectric layer directly above the alignment mark and covers the area surrounding the trench. Thereafter, a global planarization is carried out to remove the top portion of the cap layer. Finally, the remaining portion of the cap layer is removed to expose the dielectric layer so that an alignment mark re-emerges on top of the dielectric layer.

Abstract: In this method of reconstructing an alignment mark during shallow trench isolation process, a mask layer is formed on the substrate and a cap layer is further formed to fill a recess within the mask layer above the alignment mark. A trench is then formed within the substrate. An insulating layer is formed to fill the trench and a CMP process is carried out to globally planarize the wafer until exposing the mask layer. The cap layer, the mask layer and the pad oxide layer are then successively removed. An isolation region is therefore formed in the trench and the alignment mark can be reconstructed.

Abstract: A method for forming shallow trench isolation region. The method includes the steps of forming spacers on the sidewalls of a patterned mask layer and a pad oxide layer, and then etching the substrate to form a trench using the mask layer and the spacers as a mask. Thereafter, a buffer layer conformal to the surface profile of the device is formed over the substrate, and then an insulation layer is formed inside the trench. The spacers can prevent the etching of the insulation layer to form recess cavities at the upper corners of the trench when the pad oxide layer is removed in an etching operation. Hence, the kink effect is prevented. The buffer layer can prevent the oxidation of trench sidewalls when the insulation layer is densified in an oxygen-filled atmosphere. Moreover, the buffer layer can also prevent sideways etching of the insulation layer when the pad oxide layer is etched.

Abstract: A process for fabricating a semiconductor device comprising a source, a drain, and a gate electrode having an increased effective gate length. A semiconductor device is fabricated by a process comprising the following steps: forming active areas separated by field oxide regions; forming a lightly doped region in each active area; forming a heavily doped p-Si (or a-Si) layer; depositing and patterning several dielectric layers to form a gate area surrounded by vertical spacers; forming a groove in the gate area and the substrate; forming a gate oxide layer in the groove and driving dopants in the doped p-Si (or a-Si) layer into the substrate to form the source and the drain; and forming a gate electrode in the groove.

Abstract: A method of manufacturing a semiconductor device with raised source/drain. This method eliminates the problem which is often experienced when the shallow junction technique is applied, in which over-etching of the source/drain region during the contact etching and the salicide process can lead to current leakages. The improved method includes the steps of forming a buffer conductive blocks on the source/drain regions which increase the thickness of source/drain regions. A related semiconductor structure made by the method has a plurality of bi-flange shape side wall spacers by which the semiconductor structure not only elevates the doped regions, it also provides an improved capability to suppress the electric bridges between the gate electrode and source/drain regions, respectively.

Abstract: A method of making a resistor begins with forming a field effect transistor on a silicon semiconductor substrate. Then a first insulating layer is deposited on the field effect transistor. The first insulating layer is etched by the photolithography and etching techniques to form a bit line contact, and a bit line is subsequently formed. Next, upon the entire structure, a second insulating layer is formed and etched by the photolithography and ion etching techniques to form a contact hole with high aspect ratio. A polysilicon layer is deposited across the contact hole and the polysilicon outside the contact hole is removed, forming a polysilicon plug in the contact hole. Then, a third insulating layer is formed and etched to form a contact hole for metallurgy. After a first metal interconnection is formed, a third insulating layer is formed upon the entire structure and then etched to form a via hole by the photolithography and plasma etching techniques.

Abstract: A method of fabricating a DRAM device having nitride/oxide or tantalum pentoxide dielectric layers. The method includes: forming field oxide regions on a substrate to define active regions; forming at each active region a MOSFET comprising a top dielectric layer; forming a contact window in the MOSFET top dielectric layer; generating a doped poly-Si bottom electrode of a capacitor in electrical connection with the MOSFET through the contact window; removing surface oxide of the bottom electrode using both chemical and inductive coupled plasma (ICP) treatments; depositing nitride/oxide dielectric layers or a tantalum pentoxide dielectric layer on the ICP-treated bottom electrode; generating a doped poly-Si top electrode of the capacitor.

Abstract: The present invention relates to a method for increasing capacity of a capacitor. The method includes forming a polysilicon spacer on sidewall of a first polysilicon electrode and then treating the polysilicon spacer with a phosphoric acid to form a roughened surface area on the polysilicon spacer and the first polysilicon electrode. By this arrangement, the overall surface area of the polysilicon spacer and the first polysilicon electrode can be increased and the capacity of a capacitor can be increased accordingly.

Abstract: A method of forming isolation region of an integrated circuit by using rough oxide mask is described. First, a layer of first dielectric is formed on the surface of a silicon substrate. The first dielectric layer is then patterned to define active device region and isolation region. Next, a very thin layer of silicon dioxide is formed over the silicon substrate surface, followed by depositing a layer of rough oxide with proper grain size overlaying the silicon dioxide layer. By using rough oxide grains as an etching mask, the silicon dioxide layer and the silicon substrate underneath are spontaneously etched to form multiple trenches in the isolation region. Next, the rough oxide grains and silicon dioxide layers are stripped. Then, filed oxidation is performed to complete the field oxide isolation formation.

Abstract: A method of manufacturing a raised source/drain semiconductor device is disclosed. When the shallow junction technique is applied, over etching of the source/drain regions during contact etching and salicide processing will lead to current leakage. The invention provides a method which comprises depositing a buffer conductive layer above the substrate and removing a portion of this layer to form buffer conductive blocks on the source/drain regions which increase the thickness of source/drain regions.

Abstract: A process for fabricating a semiconductor device comprising a source, a drain, and a gate electrode having an increased effective gate length. A semiconductor device is fabricated by a process comprising the following steps: forming active areas separated by field oxide regions; forming a lightly doped region in each active area; forming a heavily doped p-Si (or a-Si) layer; depositing and patterning several dielectric layers to form a gate area surrounded by vertical spacers; forming a groove in the gate area and the substrate; forming a gate oxide layer in the groove and driving dopants in the doped p-Si (or a-Si) layer into the substrate to form the source and the drain; and forming a gate electrode in the groove.