Abstract: The present invention is related to a process for fabricating a MOS device having a short channel. The process according to the present invention includes the steps of (a) providing a semiconductor substrate and forming a gate structure on the semiconductor substrate; (b) implanting impurities of a first charge type to the semiconductor substrate with the gate structure serving as a mask to form a first source/drain region having a predetermined impurity concentration; (c) pocket-implanting impurities of a second charge type to the resulting semiconductor substrate with the gate structure serving as a mask to form a second source/drain region having a predetermined impurity concentration; and (d) forming a gate side wall on a flank of the gate structure, and implanting impurities of the first charge type to the resulting semiconductor substrate with the gate structure and the gate side wall serving as a mask to form a third source/drain region having a predetermined impurity concentration.

Abstract: A new method for forming shallow trench isolation is disclosed herein. A pad oxide layer and a silicon nitride layer are formed on a wafer, respectively. A plurality of trenches are created in the wafer. Then, a SAC layer is formed on an N-well. A BSG layer is formed on a P-well and the N-well. A thermal process is used to form a channel stop in the P-well. Then, the BSG layer and the SAC layer are removed. Subsequently, a LPD oxide layer is deposited in the trenches. Then, a CMP process is used to polish the LPD oxide layer for planarization. The pad oxide layer and the silicon nitride layer are removed. Next, a gate oxide layer is formed on the wafer.

Abstract: A method for forming a structure of a split gate flash memory is provided. The method includes steps of: a) preparing a substrate having an oxide layer; b) forming a first conducting layer over the oxide layer; c) etching a portion of the first conducting layer to form a word line structure for the flash memory; d) forming a spacer layer over the word line structure to be a side-wall portion of a word-line protecting layer; e) oxidizing the word-line protecting layer to form a dielectric layer; and f) forming a floating gate layer over the dielectric layer.

Abstract: The present invention relates to a new process for fabricating integrated circuits, and more particularly, to a CMOS IC process method of low cost, shallow junction and no crystal defects. After the gate oxide and gate electrodes have been formed on the N-well and the P-well, an N.sup.- Lightly-Doped-Drain (N.sup.- LDD) is made, then the sidewall of the N-channel polysilicon gate and the P-channel polysilicon gate are covered with dielectric spacer. A layer of PhosphoSilicate Glass (PSG) is thereafter deposited and patterned on the N-well and the pickup area of the P-well by lithography and etching techniques. Ion implantation is used to build the P.sup.+ Source/Drain (S/D) electrode, after which the sidewall spacer of the P-channel polysilicon gate is removed and a blanket implantation of P dopant forms the P.sup.- LDD on the area of the N-well. The P-well is doped with N-type dopant with its source from PSG by high temperature diffusing and forms the N.sup.+ S/D electrode.

Abstract: A process for suppressing boron penetration in BF.sub.2.sup.+ -implanted P.sup.+ -poly-Si gates provides a nitrided layer between the oxide layer and poly-Si through use of inductively-coupled nitrogen plasma (ICNP) to form an energy barrier which the boron ion can hardly penetrate. The process includes the steps of growing an oxide layer by washing the silicon, introducing nitrogen gas into the inductively-coupled plasma (ICP) system and carrying out nitrogen plasma surface treatment at RF power of 150w to 250w; stacking polysilicon of 3000 .ANG. low pressure chemical vapor deposition (LPCVD) system; implanting BF.sub.2.sup.+ at 5.times.10.sup.15 atom/cm.sup.2 and 50 KeV; removing the surface oxide layer by annealing at 900.degree. C. for a time; and plating Al to form a MOS capacitor and measuring electric properties.