Abstract: Integrated circuit devices having improved interlayer dielectric (ILD) layer topography and methods of fabrication thereof are disclosed herein. An exemplary integrated circuit device includes a first gate structure having a first height disposed over a substrate in a first region and a second gate structure having a second height disposed over the substrate in a second region. The second height is less than the first height. A first contact etch stop layer is disposed over the first gate structure. A second contact etch stop layer disposed over the second gate structure. The first contact etch stop layer has a first thickness, the second contact etch stop layer has a second thickness, and the second thickness is greater than the first thickness. An interlayer dielectric layer is disposed over the first contact etch stop layer and the second contact etch stop layer.

Abstract: A process for making a wheel assembly for a lightweight vehicle includes the steps of: (a) providing a wheel which includes a rim having a recessed outer surface, (b) disposing a foam tire core on the wheel such that an inner annular surface of the foam tire core is in abutment with the recessed outer surface of the rim, (c) applying an adhesive agent on at least one of an inner surface of a rubber casing and an outer annular surface of the foam tire core, and (d) wrapping the rubber casing on the foam tire core such that the inner surface of the rubber casing is brought into press engagement with the outer annular surface of the foam tire core.

Abstract: Methods for improving interlayer dielectric (ILD) layer topography and resulting integrated circuit devices are disclosed herein. An exemplary method includes forming a first contact etch stop layer having a first thickness over a first region of a wafer, forming a second contact etch stop layer having a second thickness over a second region of the wafer, and forming an ILD layer over the first contact etch stop layer and the second contact etch stop layer. A first topography variation exists between the first region and the second region. The second thickness is different than the first thickness to achieve a second topography variation that is less than the first topography variation. The first topography variation can be caused by a height difference between a first gate structure disposed over the wafer in the first region and a second gate structure disposed over the wafer in the second region.

Abstract: A method for manufacturing a semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a silicon substrate. A first structure and a second structure are respectively formed on the silicon substrate and connected to each other. A limiting block is formed on the second structure and near an edge of the second structure beside the first structure. A bottom anti-reflection coating (BARC) layer is formed to blanketly cover the first structure, the second structure and the limiting block, in which the BARC layer includes a low-viscosity material, and the BARC layer overlying the top surface of the second structure has an external surface substantially parallel to the top surface of the second structure. Control gates are formed on the external surface of the BARC layer.

Abstract: Methods for improving interlayer dielectric (ILD) layer topography and resulting integrated circuit devices are disclosed herein. An exemplary method includes forming a first contact etch stop layer having a first thickness over a first region of a wafer, forming a second contact etch stop layer having a second thickness over a second region of the wafer, and forming an ILD layer over the first contact etch stop layer and the second contact etch stop layer. A first topography variation exists between the first region and the second region. The second thickness is different than the first thickness to achieve a second topography variation that is less than the first topography variation. The first topography variation can be caused by a height difference between a first gate structure disposed over the wafer in the first region and a second gate structure disposed over the wafer in the second region.

Abstract: A method for manufacturing a semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a silicon substrate. A first structure and a second structure are respectively formed on the silicon substrate and connected to each other. A limiting block is formed on the second structure and near an edge of the second structure beside the first structure. A bottom anti-reflection coating (BARC) layer is formed to blanketly cover the first structure, the second structure and the limiting block, in which the BARC layer includes a low-viscosity material, and the BARC layer overlying the top surface of the second structure has an external surface substantially parallel to the top surface of the second structure. Control gates are formed on the external surface of the BARC layer.

Abstract: A semiconductor device having semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a silicon substrate. A first structure and a second structure are respectively disposed on the silicon substrate and connected to each other. A limiting block is disposed on the second structure and near an edge of the second structure beside the first structure. A bottom anti-reflection coating (BARC) layer blanketly covering the first structure, the second structure and the limiting block, in which the BARC layer comprises a low-viscosity material, and the BARC layer overlying the top surface of the second structure has an external surface substantially parallel to the top surface of the second structure. Control gates are disposed on the external surface of the BARC layer.

Abstract: A semiconductor device includes a substrate having a source feature and a drain feature therein configured to enhance charge mobility, a gate stack directly over a portion of the source feature and a portion of the drain feature, a first salicide layer over substantially the entire source feature exposed by the gate stack, and a second salicide layer over substantially the entire drain feature exposed by the gate stack. The first salicide layer has a germanium concentration greater than about 0% by weight and less than about 3% by weight. The second salicide layer has a germanium concentration greater than about 0% by weight and less than about 3% by weight.

Abstract: A semiconductor device having semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a silicon substrate. A first structure and a second structure are respectively disposed on the silicon substrate and connected to each other. A limiting block is disposed on the second structure and near an edge of the second structure beside the first structure. A bottom anti-reflection coating (BARC) layer blanketly covering the first structure, the second structure and the limiting block, in which the BARC layer comprises a low-viscosity material, and the BARC layer overlying the top surface of the second structure has an external surface substantially parallel to the top surface of the second structure. Control gates are disposed on the external surface of the BARC layer.

Abstract: A method of cleaning and drying a semiconductor wafer including inserting a semiconductor wafer into a chamber of a cleaning tool, spinning the semiconductor wafer in a range of about 300 revolutions per minute to about 1600 revolutions per minute, and simultaneously spraying the semiconductor wafer with de-ionized water and a mixture of isopropyl alcohol and nitrogen.

Abstract: A method of fabricating a semiconductor structure includes forming first and second features in a scribe region of a semiconductor substrate in which the first and second features are electrically isolated from each other; forming an interlayer dielectric layer over the first and second features; and forming a first contact in the interlayer dielectric layer and connected to the first feature and a second contact in the interlayer dielectric layer and connected to the second feature.

Abstract: A method of fabricating a semiconductor structure includes forming first and second features in a scribe region of a semiconductor substrate in which the first and second features are electrically isolated from each other; forming an interlayer dielectric layer over the first and second features; and forming a first contact in the interlayer dielectric layer and connected to the first feature and a second contact in the interlayer dielectric layer and connected to the second feature.

Abstract: A method of fabricating a semiconductor structure includes forming first and second features in a scribe region of a semiconductor substrate in which the first feature has a first electrical resistance, the second feature has a second electrical resistance, and the first electrical resistance is different form the second electrical resistance; forming an interlayer dielectric layer over the first and second features; and forming a first contact in the interlayer dielectric layer and connected to the first feature and a second contact in the interlayer dielectric layer and connected to the second feature.

Abstract: A method of forming a semiconductor device includes forming a gate stack over a first portion of a source and a first portion of a drain. The method includes depositing a first cap layer comprising silicon over a second portion of the source and depositing a second cap layer comprising silicon over a second portion of the drain. The method includes depositing a metal layer over the gate stack, the first cap layer and the second cap layer. The method includes annealing the semiconductor device until all of the silicon in the first and second cap layers reacts with metal from the metal layer, wherein the annealing causes metal from the metal layer to react with silicon in the first cap layer, the second cap layer, the source, and the drain. Annealing the semiconductor device includes forming a salicide layer having a germanium concentration less than 3% by weight.

Abstract: A method of fabricating a gate cap layer includes providing a substrate with an interlayer dielectric disposed thereon, wherein a recess is disposed in the interlayer dielectric and a metal gate fills in a lower portion of the recess. Later, a cap material layer is formed to cover the interlayer dielectric and fill in an upper portion of the recess. After that, a first sacrifice layer and a second sacrifice layer are formed in sequence to cover the cap material layer. The first sacrifice layer has a composition different from a composition of the cap material layer. The second sacrifice layer has a composition the same as the composition of the cap material layer. Next, a chemical mechanical polishing process is preformed to remove the second sacrifice layer, the first sacrifice layer and the cap material layer above a top surface of the interlayer dielectric.

Abstract: A method of fabricating fin structure is provided. A patterned catalyst layer and a patterned passivation layer extending along a first direction are formed on a substrate. The patterned passivation layer is located on the patterned catalyst layer. A carbon layer is formed on at least one side of the patterned catalyst layer and includes hollow carbon tubes arranged along the first direction. Each hollow carbon tube extends along a second direction. A removal process is performed to remove the top and a portion of the bottom of each hollow carbon tube closest to the substrate, so that remnants are left and serve as a mask layer. Two adjacent remnants form a stripe pattern extending along the second direction. The patterned passivation layer and the patterned catalyst layer are removed. The pattern of the mask layer is transferred to the substrate to form fin structures. The mask layer is removed.

Abstract: A detector for measuring scanning ion beams in radiation therapy sequentially includes a first high voltage electrode, a first spacing member, and a segmented electrode. The first spacing member is connected to the first high voltage electrode and the segmented electrode to form a first ionization cavity. The first ionization cavity is formed with a plurality of first reading electrodes and a plurality of second reading electrodes therein. A second spacing member and a second high voltage electrode are further sequentially disposed. The second spacing member is connected to the second high voltage electrode and the segmented electrode to form a second ionization cavity. The first reading electrodes and the second reading electrodes are respectively formed in the first ionization cavity and the second ionization cavity. With the first reading electrodes and the second reading electrodes in different directions, highly accurate space resolution, space dosage and scanning speed are achieved.

Abstract: The present invention relates to a non-contact continuous type sensing device for a flowmeter and a sensing method thereof. The flowmeter includes a movable member that is connected to an operating member and that is driven by a fluid to move, thereby moving the operating member. A projector is mounted above the operating member and projects signals onto the operating member. At least two regions are defined in a side of the operating member facing the projector. At least one of the at least two regions includes metal material to reflect the signals projected thereon. A signal density in a space between the projector and the operating member is changed when the operating member is passing through the space, such that the projection power of the projector is affected to thereby sense a movement condition of the operating member and to thereby continuously know a flowing condition of the fluid.

Abstract: A method for estimating a channel state of an audio/video signal includes: estimating a first response and a second response according to the audio/video signal, wherein the first response corresponds to an echo path and the second response corresponds to a reference path; calculating a plurality of phase differences at a plurality of time points between the first response and the second response; determining whether the echo path is a Doppler path according to the phase differences; and when it is determined that the echo path is the Doppler path, calculating a phase rotation frequency of the Doppler path according to a difference between at least two of the phase differences.

Abstract: A signal detection method detects a digital signal in a channel. The signal detection method includes: performing a power operation and a frequency transformation operation on a signal of the channel to obtain at least one frequency-domain power set; and determining whether the channel carries the digital signal according to the at least one frequency-domain power set.