Patents by Inventor Chih-Hung Chen

Chih-Hung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210019071
    Abstract: Methods, systems, and devices for one or more clock domain crossing queues are described. A queue can receive, from a first clock domain, a first command to store data in the queue. The queue can store the data at a first location indicated by a first pointer. The queue can receive, from the first clock domain, a second command to cause the second clock domain to retrieve the data from the queue. The queue can generate, based on receiving the second command, a third command synchronized with a clock of the second clock domain and to cause the second clock domain to retrieve the data. The queue can retrieve the data from the first location in the queue indicated by a second pointer associated with retrieving data based at least in part on generating the third command. The queue can transmit, to the second clock domain, the data.
    Type: Application
    Filed: June 30, 2020
    Publication date: January 21, 2021
    Inventors: Yueh-Hung Chen, Chih-Kuo Kao, Ying Yu Tai, Jiangli Zhu
  • Publication number: 20210020449
    Abstract: A chemical mechanical planarization (CMP) system including a capacitive deionization module (CDM) for removing ions from a solution and a method for using the same are disclosed. In an embodiment, an apparatus includes a planarization unit for planarizing a wafer; a cleaning unit for cleaning the wafer; a wafer transportation unit for transporting the wafer between the planarization unit and the cleaning unit; and a capacitive deionization module for removing ions from a solution used in at least one of the planarization unit or the cleaning unit.
    Type: Application
    Filed: July 18, 2019
    Publication date: January 21, 2021
    Inventors: Te-Chien Hou, Yu-Ting Yen, Cheng-Yu Kuo, Chih Hung Chen, William Weilun Hong, Kei-Wei Chen
  • Patent number: 10883667
    Abstract: An LED light source module is provided, including a substrate, a protective layer, a first conductive terminal, a second conductive terminal, at least one auxiliary structure, and a light-emitting member. The protective layer is disposed on the substrate and has an opening. The first conductive terminal, the second conductive terminal, and the auxiliary structure are disposed on the substrate and accommodated in the opening, wherein the auxiliary structure is disposed between the first conductive terminal and the second conductive terminal. The light-emitting member has a first electrode and a second electrode, respectively electrically connected to the first conductive terminal and the second conductive terminal. The auxiliary structure is disposed between the light-emitting member and the substrate. A method for manufacturing the aforementioned LED light source module is also provided.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: January 5, 2021
    Assignees: RADIANT OPTO-ELECTRONICS (SUZHOU) CO., LTD, RADIANT OPTO-ELECTRONICS CORPORATION
    Inventors: Chih-Hsien Chung, Hsiu-Hung Yeh, Ching-Yuan Chen, Yen-Chuan Chu
  • Publication number: 20200411363
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming first and second well regions with different conductivity types in a semiconductor substrate. A well interface is formed between the first and second well regions. The method also includes patterning the semiconductor substrate to form a first fin structure in the first well region, a second fin structure in the second well region, and a first trench between the first and second fin structures. The first trench exposes the well interface in the semiconductor substrate. The method further includes forming insulating spacers on opposite sidewalls of the first trench and etching the semiconductor substrate below the first trench using the insulating spacers as an etch mask, to form a second trench below the first trench. In addition, the method includes filling the first and second trenches with an insulating material.
    Type: Application
    Filed: September 11, 2020
    Publication date: December 31, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Tien-Shao CHUANG, Kuang-Cheng TAI, Chun-Hung CHEN, Chih-Hung HSIEH, Kuo-Hua PAN, Jhon-Jhy LIAW
  • Publication number: 20200410198
    Abstract: A fingerprint sensor includes a die, a plurality of conductive structures, an encapsulant, a plurality of conductive patterns, a first dielectric layer, a second dielectric layer, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The conductive patterns are over the die and are electrically connected to the die and the conductive structures. Top surfaces of the conductive patterns are flat. The first dielectric layer is over the die and the encapsulant. A top surface of the first dielectric layer is coplanar with top surfaces of the conductive patterns. The second dielectric layer covers the first dielectric layer and the conductive patterns. The redistribution structure is over the rear surface of the die.
    Type: Application
    Filed: September 10, 2020
    Publication date: December 31, 2020
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ying-Cheng Tseng
  • Publication number: 20200411561
    Abstract: A display apparatus includes a wireless transmission unit and a display panel. The display panel includes a substrate, a plurality of pixel units and a signal line. The substrate includes a display region and a periphery region. The periphery region surrounds the display region. The pixel units are disposed on the display region. Each of the pixel units includes an active device and a pixel electrode. The active device is electrically connected to the pixel electrode. The signal line is on the periphery region. As viewed from a top view, the signal line has an annular shape having a gap and surrounds the display region.
    Type: Application
    Filed: June 22, 2020
    Publication date: December 31, 2020
    Inventors: Chia-Chi CHANG, Chih-Chun CHEN, Chi-Ming WU, Yi-Ching WANG, Jia-Hung CHEN, Bo-Tsang HUANG, Wei-Yueh KU
  • Patent number: 10879306
    Abstract: A micro semiconductor structure is provided. The micro semiconductor structure includes a substrate, a plurality of micro semiconductor devices disposed on the substrate, and a first supporting layer disposed between the substrate and the micro semiconductor devices. Each of the micro semiconductor devices has a first electrode and a second electrode disposed on a lower surface of the micro semiconductor devices. The lower surface includes a region, wherein the region is between the first electrode and the second electrode. An orthographic projection of the first supporting layer on the substrate at least overlaps an orthographic projection of a portion of the region on the substrate. The first supporting layer directly contacts the region.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: December 29, 2020
    Assignee: PLAYNITRIDE DISPLAY CO., LTD.
    Inventors: Chih-Ling Wu, Ying-Tsang Liu, Pei-Hsin Chen, Yi-Chun Shih, Yi-Ching Chen, Yu-Chu Li, Huan-Pu Chang, Yu-Yun Lo, Yi-Min Su, Tzu-Yang Lin, Yu-Hung Lai
  • Patent number: 10879221
    Abstract: A package-on-package structure includes a first package, a second package and first intermetallic features. The first package includes at least one semiconductor die, an insulating encapsulant, a redistribution layer and conductive pads. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the insulating encapsulant. The conductive pads are located at a surface of the insulating encapsulant. The second package is stacked on the first package and electrically connected to the conductive pads through connectors. The first intermetallic features are sandwiched in between the conductive pads and the connectors and have a control region and a growth region. The connectors are connected to the control region, and the growth region spreads out from a periphery of the control region such that the spreading of the growth region extends away from the conductive pads in a direction towards the semiconductor die.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Ti Lu, Chih-Hua Chen, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin
  • Patent number: 10880296
    Abstract: Security functions for a memory corresponding to a smart security storage may be facilitated or executed through operation of utility application corresponding to a smart device. For example, encryption/decryption of data stored on the memory may be facilitated or executed by a security module under control of an access application corresponding to the smart device. Data securely stored on the memory may be explored and accessed by the smart device or a host computing device under control of the access application.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: December 29, 2020
    Assignee: KINGSTON DIGITAL INC.
    Inventors: Ben Wei Chen, Chih-Hung Wu
  • Patent number: 10879173
    Abstract: A semiconductor structure is disclosed that includes a first conductive line, a first conductive segment, a second conductive segment, and a gate. The first conductive segment is electrically coupled to the first conductive line through a conductive via. The second conductive segment is configured to electrically couple the first conductive segment with a third conductive segment disposed over an active area. The gate is disposed under the second conductive segment and disposed between first conductive segment and the third conductive segment. The first conductive line and the second conductive segment are disposed at two sides of the conductive via respectively.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Hung Shen, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Wei-Cheng Lin
  • Patent number: 10878915
    Abstract: A method for programming a memory device is provided. The memory device includes first to fourth memory cells, in which the first and second memory cells share a first erase gate, and the third and fourth memory cells share a second erase gate. The method includes applying a first voltage to control gates of the first and third memory cell; applying a second voltage to control gates of the second and fourth memory cells, in which the first voltage is higher than the second voltage; applying a third voltage to a select gate of the first memory cell; and applying a fourth voltage to select gates of the second to fourth memory cell, in which the third voltage is higher than the fourth voltage.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Pin Chang, Hsien-Jung Chen, Chien-Hung Liu, Chih-Wei Hung
  • Patent number: 10875149
    Abstract: A slurry dispensing unit for a chemical mechanical polishing (CMP) apparatus is provided. The slurry dispensing unit includes a nozzle, a mixer, a first fluid source, and a second fluid source. The nozzle is configured to dispense a slurry. The mixer is disposed upstream of the nozzle. The first fluid source is connected to the mixer through a first pipe and configured to provide a first fluid including a first component of the slurry. The second fluid source is connected to the mixer through a second pipe and configured to provide a second fluid including a second component of the slurry, wherein the second component is different from the first component.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kei-Wei Chen, Chih-Hung Chen, Ying-Lang Wang
  • Publication number: 20200395275
    Abstract: A device includes a die paddle and a plurality of leads. The leads surround the die paddle. Each of the leads includes an inner lead portion adjacent to and spaced apart from the die paddle, an outer lead portion opposite to the inner lead portion and a bridge portion between the inner lead portion and the outer lead portion. The inner lead portion has an upper bond section connected to the bridge portion and a lower support section below the upper bond section. A sum of a thickness of the upper bond section and a thickness of the lower support section is greater than a thickness of the bridge portion.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 17, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuang-Hsiung CHEN, Chih-Hung HSU, Mei-Lin HSIEH, Yi-Cheng HSU, Yuan-Chun CHEN, Yu-Shun HSIEH, Ko-Pu WU
  • Patent number: 10866524
    Abstract: A method includes selecting a group of wafers, each of the wafers having a resist pattern; selecting a group of fields for each of the wafers; selecting one or more points on each of the fields; measuring overlay errors on the resist pattern at locations associated with the one or more points selected on the respective wafers; and generating a combined overlay correction map based on measurements of the overlay errors on the wafers. At least one of the selecting of the group of wafers, the selecting of the group of fields, and the selecting of the one or more points is based on a computer-generated model.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yang-Hung Chang, Chih-Ming Ke, Kai-Hsiung Chen
  • Patent number: 10869323
    Abstract: The present invention discloses a Wireless Local Area Network (WLAN) and Bluetooth (BT) device including a WLAN circuit and a BT circuit. The WLAN circuit starts a WLAN slot according to a beacon of a beacon signal from an access point and executes WLAN communication. The WLAN slot ends after a measured reception time point of the beacon so as to prevent missing the beacon. The BT circuit starts a BT slot after the end of the WLAN slot and executes BT communication. If the BT slot is shorter than the period of the beacon signal minus the WLAN slot, the WLAN circuit earns additional time to start an extended WLAN slot after the end of the BT slot for carrying on the WLAN communication. The extended WLAN slot is not longer than the period of the beacon signal minus the sum of the WLAN and BT slots.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: December 15, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chih-Hung Tsai, Chien-Yu Chen
  • Patent number: 10868148
    Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: December 15, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Chang Lin, Bo-Han Huang, Chih-Chung Chen, Chun-Hsien Lin, Shih-Hung Tsai, Po-Kuang Hsieh
  • Patent number: 10868250
    Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chi Tu, Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang, Sheng-Hung Shih, Wen-Chun You, Wen-Ting Chu, Yu-Wen Liao
  • Publication number: 20200384123
    Abstract: Disclosed herein is a method for treating a cancer, the method includes following operations. A pharmaceutical composition is administered to a subject in need. The pharmaceutical composition includes a medium and a plurality of cisplatin-loaded microbubbles dispersed in the medium. Each cisplatin-loaded microbubble includes a shell portion and a core portion. The shell portion includes a plurality of albumin molecules and a plurality of first cisplatin molecules covalently bonding to the albumin molecules. The core portion is surrounded by the shell portion, wherein the core portion includes a mixture of inert gas and a plurality of second cisplatin molecules. Ultrasound energy is then applied to a tumor of the subject to break the cisplatin-loaded microbubbles.
    Type: Application
    Filed: June 7, 2019
    Publication date: December 10, 2020
    Inventors: Chih-Hung Wang, Ai-Ho Liao, Hang-Kang Chen
  • Patent number: 10857852
    Abstract: An adaptive radiant heating system regulates a climate inside a motor vehicle cabin having a seat for a vehicle occupant. The system includes radiant heating tiles arranged proximate the seat and powered by an energy storage device. The system also includes a first sensor for detecting a position of the occupant and generating a first signal indicative thereof. The system additionally includes a second sensor for detecting a temperature within the cabin and generating a second signal indicative thereof. The system furthermore includes an electronic controller in operative communication with the tiles and the first and second sensors, and configured to regulate the climate proximate the seat via selective control of the tiles. The controller is configured to receive the first and second signals and activate at least one of the tiles in response to the first and second signals, to thereby regulate the climate proximate the seat.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: December 8, 2020
    Assignee: GM Global Technology Operations LLC
    Inventors: Chih-hung Yen, Kuo-huey Chen, Taeyoung Han, Bahram Khalighi, Shailendra Kaushik
  • Patent number: 10862029
    Abstract: Some embodiments relate to a device. The device includes a top electrode and a via disposed over the top electrode. A peripheral upper surface of the top electrode is above a central upper surface of the top electrode, and a tapered inner sidewall of the top electrode connects the peripheral upper surface to the central upper surface. The via establishes electrical contact with the tapered inner sidewall but is spaced apart from the central upper surface.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsia-Wei Chen, Wen-Ting Chu, Kuo-Chi Tu, Chih-Yang Chang, Chin-Chieh Yang, Yu-Wen Liao, Wen-Chun You, Sheng-Hung Shih