Patents by Inventor Chih-Hung Chen

Chih-Hung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230267264
    Abstract: A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 24, 2023
    Inventors: I-Shuo Liu, Chih-Chun Hsia, Hsin-Ting Chou, Kuanhua Su, William Weilun Hong, Chih Hung Chen, Kei-Wei Chen
  • Patent number: 11735379
    Abstract: A keyswitch assembly includes a switch module, a support mechanism, a blocking mechanism, an enhancing light source, and a backlight source. The switch module includes a substrate, a signal generator, and a signal sensor. The signal generator generates a sensing signal. The signal sensor receives the sensing signal to obtain a sensing strength. The support mechanism is disposed on the substrate. The blocking mechanism is disposed on the substrate and has a light-permeable portion. A portion of the blocking mechanism inserts into or escapes from a gap between the signal generator and the signal sensor. The backlight source is disposed on the substrate and located outside the vertical projection of the blocking mechanism on the substrate. The enhancing light source is disposed on the substrate and located within the vertical projection of the blocking mechanism on the substrate and corresponds to the light-permeable portion.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: August 22, 2023
    Assignee: DARFON ELECTRONICS CORP.
    Inventors: Li-Te Chang, Chih-Hung Chen, Yen-Ting Chen
  • Patent number: 11721500
    Abstract: A keyswitch assembly includes a switch module, a support mechanism, and a blocking mechanism. The switch module includes a substrate, a signal generator, and a signal sensor. The signal generator provides a sensing signal. The signal sensor receives the sensing signal to obtain a sensing intensity. The support mechanism is disposed on the substrate. A top portion of the support mechanism moves in response to a pressing force. The blocking mechanism includes a pivoting portion rotatably disposed on the substrate, a connecting piece extending from the pivoting portion and movably connected to the support mechanism to be driven by the top portion to swivel relative to the substrate, and a blocking piece extending from the pivoting portion and driven by the connecting piece to be inserted into or escape from the gap between the signal generator and the signal sensor to change the magnitude of the sensing intensity.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: August 8, 2023
    Assignee: DARFON ELECTRONICS CORP.
    Inventors: Li-Te Chang, Chih-Hung Chen, Yen-Ting Chen
  • Publication number: 20230203474
    Abstract: A compound, a solid carrier including the same and a method for preparing a nucleic acid are provided. The compound has a structure represented by Formula (1) as follows. In Formula (1), the definition of Y1, Y2, Z and * are the same as defined in the detailed description.
    Type: Application
    Filed: December 26, 2022
    Publication date: June 29, 2023
    Applicant: Industrial Technology Research Institute
    Inventors: Ming-Chun Lin, Hui-Ling Cheng, Chun-Ting Lai, Hua-Cheng Chou, Wei-Chin Huang, Chih-Hung Chen, Shu-Feng Chen
  • Patent number: 11685013
    Abstract: A polishing pad includes a pad layer and one or more polishing structures over an upper surface of the pad layer, where each of the one or more polishing structures has a pre-determined shape and is formed at a pre-determined location of the pad layer, where the one or more polishing structures comprise at least one continuous line shaped segment extending along the upper surface of the pad layer, where each of the one or more polishing structures is a homogeneous material.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: June 27, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Hung Chen, Kei-Wei Chen, Ying-Lang Wang
  • Patent number: 11679469
    Abstract: A chemical mechanical planarization (CMP) tool includes a platen and a polishing pad attached to the platen, where a first surface of the polishing pad facing away from the platen includes a first polishing zone and a second polishing zone, where the first polishing zone is a circular region at a center of the first surface of the polishing pad, and the second polishing zone is an annular region around the first polishing zone, where the first polishing zone and the second polishing zone have different surface properties.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Michael Yen, Kao-Feng Liao, Hsin-Ying Ho, Chun-Wen Hsiao, Sheng-Chao Chuang, Ting-Hsun Chang, Fu-Ming Huang, Chun-Chieh Lin, Peng-Chung Jangjian, Ji James Cui, Liang-Guang Chen, Chih Hung Chen, Kei-Wei Chen
  • Patent number: 11675953
    Abstract: A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Shuo Liu, Chih-Chun Hsia, Hsin-Ting Chou, Kuanhua Su, William Weilun Hong, Chih Hung Chen, Kei-Wei Chen
  • Patent number: 11631618
    Abstract: Various embodiments provide a thickness sensor and method for measuring a thickness of discrete conductive features, such as conductive lines and plugs. In one embodiment, the thickness sensor generates an Eddy current in a plurality of discrete conductive features, and measures the generated Eddy current generated in the discrete conductive features. The thickness sensor has a small sensor spot size, and amplifies peaks and valleys of the measured Eddy current. The thickness sensor determines a thickness of the discrete conductive features based on a difference between a minimum amplitude value and a maximum amplitude value of the measured Eddy current.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: April 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih Hung Chen, Kei-Wei Chen, Ying-Lang Wang
  • Patent number: 11621342
    Abstract: In an embodiment, a method includes: performing a self-limiting process to modify a top surface of a wafer; after the self-limiting process completes, removing the modified top surface from the wafer; and repeating the performing the self-limiting process and the removing the modified top surface from the wafer until a thickness of the wafer is decreased to a predetermined thickness.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: April 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Hung Chen, Kei-Wei Chen, Ying-Lang Wang
  • Publication number: 20230095741
    Abstract: The present disclosure provides a wet chemical heating system and a method of transporting wet chemical. The method includes providing a wet chemical in a conduit, heating the wet chemical by a first radiative heating unit at a first portion of the conduit, including elevating a temperature of the wet chemical at the first portion of the conduit to a first temperature greater than a second temperature of the first portion of the conduit; and dispensing the wet chemical from the conduit.
    Type: Application
    Filed: December 1, 2022
    Publication date: March 30, 2023
    Inventors: JI JAMES CUI, CHIA-HSUN CHANG, CHIH HUNG CHEN, LIANG-GUANG CHEN, TZU KAI LIN, CHYI SHYUAN CHERN, KEITH KUANG-KUO KOAI
  • Publication number: 20230064958
    Abstract: A method of cleaning and polishing a backside surface of a semiconductor wafer is provided. The method includes placing an abrasive brush, comprising an abrasive tape wound around an outer surface of a brush member of the abrasive brush, on the backside surface of the semiconductor wafer. The method also includes rotating the brush member to polish the backside surface of the semiconductor wafer by abrasive grains formed on the abrasive tape and to clean the backside surface of the semiconductor wafer by the brush member which is not covered by the abrasive tape.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: KEI-WEI CHEN, CHIH HUNG CHEN
  • Patent number: 11574911
    Abstract: The present application discloses a method for fabricating a semiconductor device with a protruding contact. The method includes providing a substrate; forming a bit line structure on the substrate; forming a capacitor contact structure next to the bit line structure; recessing a top surface of the bit line structure; and forming a landing pad layer covering a portion of a top surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: February 7, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chiang-Lin Shih, Chih-Hung Chen, Szu-Yao Chang
  • Publication number: 20230021149
    Abstract: Some implementations described herein relate to dispensing a slurry onto a polishing pad for a chemical-mechanical planarization (CMP) process. These implementations also involve rotating the polishing pad while the slurry is dispensed onto the polishing pad. Rotation of the polishing pad results in a traversal of the slurry radially outward toward a polishing pad outer edge of the polishing pad. The polishing pad includes a plurality of groove segments and a geometric patterns formed by the plurality of the groove segments impede the flow of the slurry to the polishing pad outer edge.
    Type: Application
    Filed: November 2, 2021
    Publication date: January 19, 2023
    Inventors: Te-Chien HOU, Chih Hung CHEN, Shich-Chang SUEN, Liang-Guang CHEN, Wen-Pin LIAO, Kei-Wei CHEN
  • Publication number: 20230007782
    Abstract: A manufacturing method of a circuit board includes: providing a first double-sided copper laminate including a dielectric layer, a first copper foil layer and a copper plating layer wherein the dielectric layer, wherein the dielectric layer defines a groove, the copper plating layer includes a first copper plating portion in the groove and a second copper plating portion beside the first copper plating portion. A double-sided circuit substrate including base layer and two first wiring layers is provided, wherein each first wiring layer includes a signal line. Conductive paste blocks are disposed in the base layer and on both sides of the signal line; and a first double-sided copper laminate is stacked on each side of the double-sided circuit substrate, disposing the signal line in the groove. The conductive paste blocks are pressed electrically connect same to the second copper plating portions. The present disclosure further provides a circuit board.
    Type: Application
    Filed: May 20, 2020
    Publication date: January 5, 2023
    Inventors: CHAO PENG, KE HE, CHIH-HUNG CHEN
  • Publication number: 20220415665
    Abstract: A chemical mechanical planarization system includes a chemical mechanical planarization pad that rotates during a chemical mechanical planarization process. A chemical mechanical planarization head places a semiconductor wafer in contact with the chemical mechanical planarization pad during the process. A slurry supply system supplies a slurry onto the pad during the process. A pad conditioner conditions the pad during the process. An impurity removal system removes debris and impurities from the slurry.
    Type: Application
    Filed: June 23, 2021
    Publication date: December 29, 2022
    Inventors: Te-Chien HOU, Po-Chin NIEN, Chih Hung CHEN, Ying-Tsung CHEN, Kei-Wei CHEN
  • Patent number: 11517995
    Abstract: The present disclosure provides a wet chemical heating system, including a first conduit for transporting wet chemical, a dispensing head connected to the first conduit, and a radiative heating element configured to heat the wet chemical in the first conduit and positioned at an upper stream of the dispensing head.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: December 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ji James Cui, Chia-Hsun Chang, Chih Hung Chen, Liang-Guang Chen, Tzu Kai Lin, Chyi Shyuan Chern, Keith Kuang-Kuo Koai
  • Publication number: 20220382947
    Abstract: A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout.
    Type: Application
    Filed: July 26, 2022
    Publication date: December 1, 2022
    Inventors: I-Shuo Liu, Chih-Chun Hsia, Hsin-Ting Chou, Kuanhua Su, William Weilun Hong, Chih Hung Chen, Kei-Wei Chen
  • Patent number: 11482525
    Abstract: The present disclosure provides a method for manufacturing a semiconductor structure with capacitor landing pads. The method includes the following operations: providing a semiconductor substrate; forming a bit line structure protruding from the semiconductor substrate; depositing a landing pad layer to cover the bit line structure; planarizing a top surface of the landing pad layer; limning a trench in the landing pad layer to form the capacitor landing pads; forming an air gap within a sidewall of the bit line structure; and filling a first dielectric layer in the trench to seal the air gap.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: October 25, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chih-Hung Chen
  • Patent number: D982216
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: March 28, 2023
    Assignee: LIVINGSTYLE ENTERPRISES LIMITED
    Inventors: Ming-Yun Chen, Chih-Hung Chen
  • Patent number: D982217
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: March 28, 2023
    Assignee: LIVINGSTYLE ENTERPRISES LIMITED
    Inventors: Ming-Yun Chen, Chih-Hung Chen