FIELD EFFECT TRANSISTOR WITH FIN STRUCTURE

Abstract

A FET with a fin structure includes a substrate, an isolation structure and a gate structure. The substrate includes at least one fin structure. The fin structure includes two source/drain regions and a gate channel region between the two source/drain regions. The isolation structure is disposed on the substrate and surrounds the fin structure to expose an upper portion of the fin structure. A width of the gate channel region of the exposed upper portion of the fin structure is less than each of widths of the source region and the drain region. A gate structure covering two sidewalls of the gate channel region of the exposed upper portion of the fin structure is formed. Two sidewalls of the gate structure contact two facing sidewalls of the two source/drain regions, respectively.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a division of U.S. application Ser. No. 13/284,987, filed Oct. 31, 2011, the disclosure of which is hereby incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a field effect transistor (FET) with a fin structure, and more particularly to a field effect transistor fabricated through a damascene-like process.

2. Description of the Prior Art

With the trend of scaling down the size of metal oxide semiconductor transistors (MOS) in the industry, three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (Fin-FET) has been developed to replace planar MOS transistors. The three-dimensional structure of a fin-FET increases the overlapping area between the gate and the fin structure of the silicon substrate, and accordingly, the channel region is more effectively controlled. The short channel effect which miniaturized devices may encounter is therefore reduced. The channel region is also wider under the same gate length, and thus the current between the source and the drain is increased.

Since the fin-FET devices have the aforesaid advantages, there is still a need for novel fin-FET devices and methods of fabricating the same to improve performance.

SUMMARY OF THE INVENTION

An objective of the present invention is to provide a FET with a fin structure, in which, a width of a gate channel region of an exposed upper portion of the fin structure is less than each of widths of the source region and the drain region and a gate structure is well aligned with the gate channel region.

According to one aspect of an embodiment of the present invention, the FET with a fin structure includes a substrate, an isolation structure and a gate structure. The substrate includes at least one fin structure. The fin structure includes two source/drain regions and a gate channel region between the two source/drain regions. The isolation structure is disposed on the substrate and surrounds the fin structure to expose an upper portion of the fin structure. A width of the gate channel region of the exposed upper portion of the fin structure is less than each of widths of the source region and the drain region. A gate structure covering two sidewalls of the gate channel region of the exposed upper portion of the fin structure is formed. Two sidewalls of the gate structure contact two facing sidewalls of the two source/drain regions, respectively.

In the present invention, a process similar to damascene is utilized to form a trench within an insulation layer to expose an upper portion of a gate channel region of a fin structure, and thereafter agate structure covering the gate channel region is formed within the trench. Accordingly, in the process, the gate structure and the gate channel region are self-aligned with each other. Furthermore, in the process, the insulation layer may include amorphous material to avoid a rough surface due to crystal grains, and accordingly the trench may have a smooth surface and the resultant gate structure may have a relative fine and straight edge with respect to a conventional gate structure obtained from patterning directly through an etching process. Furthermore, in a certain embodiment, a trim process may be further performed to reduce the width of the exposed upper portion of the fin structure; while the source/drain regions may be still in the original width. Accordingly, the problems of short channel effect, such as drain induced barrier lowering (DIBL), sub-threshold slope and Vt roll-off effect, can be improved. Furthermore, the gate structure and the gate channel region are well self-aligned with each other, such that, the two sidewalls of the gate structure contact two sidewalls, which face each other, of the two source/drain regions S/D, respectively. No gap is between the gate structure and the source/drain region. Accordingly, in addition that the problems of short channel effect are improved, a low parasitic resistance between the gate structure and the source/drain can be also obtained.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 to 8 are schematic diagrams illustrating a method of fabricating a FET with a fin structure according to an embodiment of the present invention, in which, FIGS. 1 to 5, 7 and 8 are schematic cross-sectional views and FIG. 6 is a perspective view;

FIG. 9 is a schematic cross-sectional view illustrating a FET with a fin structure according to another embodiment of the present invention;

FIG. 10 is a schematic cross-sectional view illustrating a FET with a fin structure according to still another embodiment of the present invention;

FIG. 11 is a schematic plan view illustrating a FET with a fin structure according to an embodiment of the present invention; and

FIG. 12 is a schematic perspective view illustrating a FET with a fin structure according to an embodiment of the present invention.

DETAILED DESCRIPTION

Referring to FIGS. 1 to 8, a method of fabricating a FET with a fin structure according to an embodiment of the present invention is described hereinafter. First, referring to FIG. 1, a substrate 10, such as semiconductor substrate including for example a silicon substrate, is provided. At least one fin structure 12 is formed on the substrate. The fin structures 12 may be formed, for example, by means of etching the original substrate 10 through a patterned hard mask 14 formed thereon.

Thereafter, according to one feature of the present invention, a planar insulation layer is formed on the substrate to cover the fin structure. The insulation layer is partially removed to a depth to forma trench. The trench is allowed to intersect the fin structure both in their lengthwise direction, such that an upper portion of the fin structure is exposed to the trench. The way for partially removing the insulation layer to a desired depth may be various, for example, but not limited thereto, by means of etching the insulation layer through a patterned mask or hard mask to a desired or predetermined depth to form a trench within the insulation layer; or by means of disposing an etch stop layer between two insulation layers at a desired depth and then carrying out an etching process through a patterned mask or hard mask; or disposing two insulation layers having different etching rates and then carrying out an etching process through a patterned mask or hard mask for a desired etch stop. FIG. 1 through FIG. 8 illustrate an embodiment using an etch stop layer between two insulation layers for forming the trench.

Still referring to FIG. 1, an insulation layer 16 is formed on the substrate 10 and higher than the fin structure 12 to cover it. The insulation layer 16 is planarized through for example a chemical mechanical polishing (CMP) process. Thereafter, referring to FIG. 2, an etching process, or referred to as etch-back process, is performed on the planar insulation layer 16 for partial removal it. This etch may be performed all over on the substrate until a desired height of upper portion of the fin structure 12 is exposed. The rest of the insulation layer 16 is denoted by the referral number 18. The insulation layer 18 may serve as an isolation structure, such as a shallow trench isolation (STI). Accordingly, the insulation layer 16 may include for example silicon oxide. The hard mask 14 may be removed or remain. FIG. 2 shows a situation that the hard mask 14 is removed.

Thereafter, referring to FIG. 3, an etch stop layer 20 is formed on the insulation layer 18 and the upper portion of the fin structure 12. Thereafter, an insulation layer 22 covering the etch stop layer 20 is formed. The insulation layer 22 may be further planarized. The etch stop layer 20 and the insulation layer 22 may independently include, for example, silicon nitride (briefly noted as SiN) or an oxide, but are not limited thereto.

Thereafter, referring to FIG. 4, the insulation layer 22 is partially removed to a depth to form a trench 24. For example, the trench may be formed by means of etching the insulation layer 22 through a patterned mask or hard mask to the depth of the etch stop layer 20. The trench 24 in its lengthwise direction (the direction x as shown in FIG. 4) and the fin structure 12 in its lengthwise direction (the direction y perpendicular to the paper as shown in FIG. 4) are allowed to intersect each other. The insulation layer 22 is etched to the depth where the etch stop layer 20 is disposed, and thus an upper portion of the fin structure 12 within the trench is exposed. This exposed portion of the fin structure 12 will serve as a gate channel. The portion of the fin structure 12 to serve source/drain regions is still covered with the insulation layer 22. The etch stop layer 20 within the trench 24 may be further removed.

In another aspect of an embodiment, instead of forming the etch stop layer 20, two insulation layers having different etching rates, i.e. having an etch selection ratio with respect to each other, are formed for an indication for stopping the etch process as aforesaid.

Thereafter, the exposed portion of the fin structure 12 may serve for a gate channel, or it may be further reduced in width through a trim process. For example, in an embodiment illustrated by FIG. 5, a trim process is performed to reduce the width of the exposed upper portion of the fin structure 12 in the trench 24. The trim process may be performed by means of for example isotropic dry or wet etch, but not limited thereto, or further reducing the width of the hard mask atop the fin structure, to further remove a thickness of the fin structure by etching. FIG. 6 is a perspective view illustrating the structure after the trim process is performed. The width of the trimmed fin structure 12 may be for example 10 to 30 nm. The height of the exposed portion of the fin structure 12 is preferably about one to five times of the width, but not limited thereto.

A gate dielectric layer (not shown) maybe formed on the exposed upper portion of the fin structure 12. Thereafter, a gate is formed in the trench 24 to cover the channel region of the fin structure 12. Various ways may be available for forming the gate. For example, referring to FIG. 7, the trench 24 may be filled with gate material utilizing for example a CVD process to become a gate material layer 26 further covering a top of the insulation layer 22. The gate material may include for example silicon or metal . When a gate dielectric layer is formed on the exposed upper portion of the fin structure 12, the later-formed gate material layer 26 will cover the gate dielectric layer. The “gate structure” herein may include a gate material layer, or may include a gate dielectric layer and a gate material layer.

Thereafter, a planarization process, such as a CMP process, is performed to planarize the surface of the gate material layer 26 to expose the insulation layer 22. Thereafter, referring to FIG. 8, the insulation layer 22 maybe removed through for example an etching process to expose the gate 28 and the portion of the fin structure 12 not covered with the gate 28. Since the insulation layer 22 may be removed and not remain in the structure, the suitable material is not limited to the material frequently used for interlayer dielectric (for example silicon oxide). Other material can be utilized as soon as it is not harmful to the processes and the structure and the purpose as described above can be attained. The rest of the etch stop layer 20 may be further removed.

A source and a drain are formed in the fin structure at two sides of the gate 28. For example, a spacer is formed on the sidewall of the gate and the source/drain regions are implanted with dopants through an ion implantation. The gate 28 covers the exposed upper portion of the fin structure 12 (including two sidewalls and top surface of the fin structure 12), and becomes a tri-gate FET configuration. Furthermore, the gate 28 and the trimmed gate channel are aligned with each other without particular alignment processes. Accordingly, it may be referred to as a self-alignment process.

As aforesaid, after the fin structure 12 is formed, the hard mask layer 14 may be removed or allowed to remain. In the situation that the hard mask layer 14 remains, a trim process can be also performed on the fin structure 12 as described above. For example, an isotropic etching process may be performed on the trench 24. Or, a trim process is performed on the hard mask 14 to reduce the width and thereafter the gate channel region is etched to reduce the width. FIG. 9 illustrates an embodiment of a FET with a fin structure and a hard mask atop the fin structure after the trim process is performed. In this embodiment, the thickness of the hard mask layer 14 may be relatively thick, and the gate structure thus formed may have a configuration similar to a tri-gate structure but possess electric properties similar to a double-gate.

FIG. 10 illustrates an embodiment varied with respect to the embodiment shown in FIG. 9. In this embodiment, the gate material layer is planarized to expose the hard mask layer 14, thereby to form a double-gate FET configuration. It is not necessary for the hard mask 14 to be thick.

In another embodiment, a sacrificial gate is formed as described aforesaid using sacrificial gate material instead of desired gate material. Thereafter, a gate replacement process is performed to replace the sacrificial gate with a desired gate structure. The gate structure may include a gate dielectric layer and a gate. For example, a sacrificial gate is formed of polysilicon, and thereafter a gate dielectric layer and a metal gate are formed through, for example, a conventional gate replacement process.

FIG. 11 shows a schematic plan view and FIG. 12 shows a schematic perspective view, both illustrating more in detail a FET with a fin structure according to one aspect of an embodiment of the present invention. It clearly indicates that the channel width W1 covered with the gate structure 30 is less than the width W2 of the source/drain region, that the width L1 of the gate structure 30 is the same as the channel length L2 of the trimmed gate channel, and that two sidewalls 32 and 34 of the gate structure 30 contact two sidewalls 36 and 38, which face each other, of the two source/drain regions S/D, respectively, without a gap existing between the sidewall 32 and the sidewall 36 or between the sidewall 34 and the sidewall 38. In other words, the two sidewalls 32 and 34 of the gate structure 30 are aligned with two edges of the channel region. The two edges of the channel region are the two edges opposite to each other in the lengthwise direction of the channel region.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. A field effect transistor with a fin structure comprising:

a substrate comprising at least one fin structure comprising two source/drain regions and a gate channel region between the two source/drain regions;

an isolation structure disposed on the substrate and surrounding the fin structure to expose an upper portion of the fin structure, wherein a width of the gate channel region of the exposed upper portion of the fin structure is less than each of widths of the source region and the drain region; and

a gate structure covering two sidewalls of the gate channel region of the exposed upper portion of the fin structure, wherein two sidewalls of the gate structure contact two facing sidewalls of the two source/drain regions, respectively.

2. The field effect transistor with a fin structure according to claim 1, further comprising a hard mask atop the gate channel region of the fin structure.

3. The field effect transistor with a fin structure according to claim 1, wherein the gate structure further covers a top of the gate channel region of the fin structure.

4. The field effect transistor with a fin structure according to claim 1, wherein the gate structure further covers the hard mask.