Patents by Inventor Chih-Kai Hsu

Chih-Kai Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10985048
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer on the first gate structure; removing the first gate structure to form a first recess; and forming a dielectric layer in the first recess.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: April 20, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Patent number: 10985264
    Abstract: A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: April 20, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chia-Jung Hsu, Yu-Hsiang Lin
  • Patent number: 10978398
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the ILD layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate.
    Type: Grant
    Filed: January 1, 2020
    Date of Patent: April 13, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Wei-Chi Cheng, Ssu-I Fu, Jyh-Shyang Jenq
  • Patent number: 10971397
    Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate is provided. The substrate includes a pixel region having a first conductive region and a logic region having a second conductive region. A dielectric layer is formed on the substrate to cover the first conductive region. A first contact opening is formed in the dielectric layer to expose the first conductive region. A doped polysilicon layer is sequentially formed in the first contact opening. A first metal silicide layer is formed on the doped polysilicon layer. A second contact opening is formed in the dielectric layer to expose the second conductive region. A barrier layer and a metal layer are respectively formed in the first contact opening and the second contact opening.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: April 6, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chia-Jung Hsu, Chun-Ya Chiu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20210050255
    Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate is provided. The substrate includes a pixel region having a first conductive region and a logic region having a second conductive region. A dielectric layer is formed on the substrate to cover the first conductive region. A first contact opening is formed in the dielectric layer to expose the first conductive region. A doped polysilicon layer is sequentially formed in the first contact opening. A first metal silicide layer is formed on the doped polysilicon layer. A second contact opening is formed in the dielectric layer to expose the second conductive region. A barrier layer and a metal layer are respectively formed in the first contact opening and the second contact opening.
    Type: Application
    Filed: September 12, 2019
    Publication date: February 18, 2021
    Applicant: United Microelectronics Corp.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chia-Jung Hsu, Chun-Ya Chiu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20210050456
    Abstract: A manufacturing method of a semiconductor device includes the following steps. An opening is formed penetrating a dielectric layer on a semiconductor substrate. A stacked structure is formed on the dielectric layer. The stacked structure includes a first semiconductor layer partly formed in the opening and partly formed on the dielectric layer, a sacrificial layer formed on the first semiconductor layer, and a second semiconductor layer formed on the sacrificial layer. A patterning process is performed for forming a fin-shaped structure including the first semiconductor layer, the sacrificial layer, and the second semiconductor layer. An etching process is performed to remove the sacrificial layer in the fin-shaped structure. The first semiconductor layer in the fin-shaped structure is etched to become a first semiconductor wire by the etching process. The second semiconductor layer in the fin-shaped structure is etched to become a second semiconductor wire by the etching process.
    Type: Application
    Filed: September 16, 2019
    Publication date: February 18, 2021
    Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chun-Ya Chiu, Chia-Jung Hsu, Yu-Hsiang Lin
  • Patent number: 10854502
    Abstract: A semiconductor device includes a gate structure on a fin-shaped structure, a single diffusion break (SDB) structure adjacent to the gate structure, a shallow trench isolation (STI) around the fin-shaped structure, and an isolation structure on the STI. Preferably, a top surface of the SDB structure is even with a top surface of the isolation structure, and the SDB structure includes a bottom portion in the fin-shaped structure and a top portion on the bottom portion.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: December 1, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20200306314
    Abstract: The present invention is related to a method for treating and/or preventing Alzheimer's disease, especially using mitochondria for treatment and/or prevention of Alzheimer's disease.
    Type: Application
    Filed: March 27, 2020
    Publication date: October 1, 2020
    Inventors: Han-Chung CHENG, Chi-Tang TU, Chih-Kai HSU
  • Publication number: 20200295160
    Abstract: A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.
    Type: Application
    Filed: April 9, 2019
    Publication date: September 17, 2020
    Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chia-Jung Hsu, Yu-Hsiang Lin
  • Publication number: 20200295542
    Abstract: A switch seat body assembling structure includes a main body for assembling with a switch component. The main body is composed of a metal head section in the form of a thin sheet structure and a nonmetal belly section. The main body is defined with an eccentric axis and has a shaft hole positioned on the eccentric axis. The metal head section has a first wall normal to or inclined from the eccentric axis and a second wall connected with the first wall and parallel to or inclined from the eccentric axis. The first and second walls together define a space. The nonmetal belly section fills the space to connect with entire sections of the first and second walls as an integrated body. The switch seat body assembling structure improves the problems that the processing and manufacturing processes are time-consuming and troublesome and the material cost is higher.
    Type: Application
    Filed: March 12, 2020
    Publication date: September 17, 2020
    Inventors: CHIH-YUAN WU, CHIH-HAO SUNG, CHIH-KAI HSU
  • Publication number: 20200294736
    Abstract: A switch seat body structure includes a main body for assembling with a switch component. The main body is composed of a metal head section in the form of a thin sheet structure and a nonmetal belly section. The main body is defined with an axis. The metal head section has a first wall normal to or inclined from the axis and a second wall connected with the first wall and parallel to or inclined from the axis. The first and second walls together define a space. The nonmetal belly section fills the space to connect with entire sections of the first and second walls as an integrated body. The switch seat body assembling structure improves the problems that the processing and manufacturing processes are time-consuming and troublesome and the material cost is higher.
    Type: Application
    Filed: March 12, 2020
    Publication date: September 17, 2020
    Inventors: CHIH-YUAN WU, CHIH-HAO SUNG, CHIH-KAI HSU
  • Patent number: 10755919
    Abstract: A method of manufacturing semiconductor devices, including the steps of providing a substrate with a first active region, a second active region and a third active region, forming dummy gates in the first active region, the second active region and the third active region, removing the dummy gates to form trenches in the first active region, the second active region and the third active region, forming a high-k dielectric layer, a first bottom barrier metal layer on the high-k dielectric layer, a second bottom barrier metal layer on the first bottom barrier metal layer, and a first work function metal layer on the second bottom barrier metal layer in the trenches, removing the first work function metal layer from the second active region and the third active region, removing the second bottom barrier metal layer from the third region, and filling up each trench with a low resistance metal.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: August 25, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chin-Hung Chen, Chi-Ting Wu, Yu-Hsiang Lin
  • Publication number: 20200203231
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer around the first gate structure; transforming the first gate structure into a first metal gate; removing the first metal gate to form a first recess; and forming a dielectric layer in the first recess.
    Type: Application
    Filed: March 2, 2020
    Publication date: June 25, 2020
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20200144100
    Abstract: A semiconductor device includes a gate structure on a fin-shaped structure, a single diffusion break (SDB) structure adjacent to the gate structure, a shallow trench isolation (STI) around the fin-shaped structure, and an isolation structure on the STI. Preferably, a top surface of the SDB structure is even with a top surface of the isolation structure, and the SDB structure includes a bottom portion in the fin-shaped structure and a top portion on the bottom portion.
    Type: Application
    Filed: January 2, 2020
    Publication date: May 7, 2020
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20200144099
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer on the first gate structure; removing the first gate structure to form a first recess; and forming a dielectric layer in the first recess.
    Type: Application
    Filed: January 2, 2020
    Publication date: May 7, 2020
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20200135647
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the ILD layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate.
    Type: Application
    Filed: January 1, 2020
    Publication date: April 30, 2020
    Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Wei-Chi Cheng, Ssu-I Fu, Jyh-Shyang Jenq
  • Publication number: 20200111871
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; and forming a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.
    Type: Application
    Filed: December 4, 2019
    Publication date: April 9, 2020
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq
  • Patent number: 10607882
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer on the first gate structure; removing the first gate structure to form a first recess; and forming a dielectric layer in the first recess.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: March 31, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Patent number: 10566285
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the ILD layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: February 18, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Wei-Chi Cheng, Ssu-I Fu, Jyh-Shyang Jenq
  • Patent number: 10546922
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. Next, a recess is formed adjacent to two sides of the gate structure, and an epitaxial layer is formed in the recess, in which a top surface of the epitaxial layer is lower than a top surface of the substrate. Next, a cap layer is formed on the epitaxial layer, in which a top surface of the cap layer is higher than a top surface of the substrate.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: January 28, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq, Tsung-Mu Yang