Abstract: A light guide structure with jagged protrusions is configured in a lighting device of a mobile vehicle. The light guide structure comprises a light injecting surface and a light emitting surface. The light injecting surface comprises a middle section and two side sections deployed respectively at opposite ends of the middle section. At least a portion of the side sections has a light guiding area. A light source module forms an irradiation area by the light guide structure, the microstructure of the light guiding area is configured to enable the light from the light guide to pass through the light injecting surface generating refraction, diffusion, or scattering, so as to reduce the generation of stray light, and improve the clarity of the beam contour.

Abstract: A semiconductor memory structure includes a ferroelectric layer and a channel layer formed over the ferroelectric layer. The structure also includes a source structure and a drain structure formed over the channel layer. The structure further includes a first isolation structure formed between the source structure and the drain structure. The source structure extends over the cap layer and towards the drain structure.

Abstract: The present invention provides a method of improving chronic obstructive pulmonary disease and obesity using traditional Chinese medicine polysaccharides and bacterial composition thereof.

Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.

Abstract: A method includes forming a bottom electrode, forming a dielectric layer, forming a Phase-Change Random Access Memory (PCRAM) region in contact with the dielectric layer, and forming a top electrode. The dielectric layer and the PCRAM region are between the bottom electrode and the top electrode. A filament is formed in the dielectric layer. The filament is in contact with the dielectric layer.

Abstract: The present disclosure relates to an integrated chip including a three-dimensional memory array. The three-dimensional memory array includes a first local line and a second local line that are elongated vertically, a first memory cell extending between the first local line and the second local line, and a second memory cell directly under the first memory cell, extending between the first local line and the second local line, and coupled in parallel with the first memory cell. The first memory cell is coupled to a first word line and the second memory cell is coupled to a second word line. The first word line and the second word line are elongated horizontally. A first global line is disposed at a first height and is elongated horizontally. A first selector extends vertically from the first local line to the first global line.

Abstract: Various embodiments of the present disclosure are directed towards a metal-ferroelectric-insulator-semiconductor (MFIS) memory device, as well as a method for forming the MFIS memory device. According to some embodiments of the MFIS memory device, a lower source/drain region and an upper source/drain region are vertically stacked. A semiconductor channel overlies the lower source/drain region and underlies the upper source/drain region. The semiconductor channel extends from the lower source/drain region to the upper source/drain region. A control gate electrode extends along a sidewall of the semiconductor channel and further along individual sidewalls of the lower and upper source/drain regions. A gate dielectric layer and a ferroelectric layer separate the control gate electrode from the semiconductor channel and the lower and upper source/drain regions.

Abstract: Various embodiments of the present application are directed towards a bipolar selector having independently tunable threshold voltages, as well as a memory cell comprising the bipolar selector and a memory array comprising the memory cell. In some embodiments, the bipolar selector comprises a first unipolar selector and a second unipolar selector. The first and second unipolar selectors are electrically coupled in parallel with opposite orientations and may, for example, be diodes or some other suitable unipolar selectors. By placing the first and second unipolar selectors in parallel with opposite orientations, the first unipolar selector independently defines a first threshold voltage of the bipolar selector and the second unipolar selector independently defines a second threshold voltage of the bipolar selector. As a result, the first and second threshold voltages can be independently tuned by adjusting parameters of the first and second unipolar selectors.

Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.

Abstract: A method for forming a thin film resistor with improved thermal stability is disclosed. A substrate having thereon a first dielectric layer is provided. A resistive material layer is deposited on the first dielectric layer. A capping layer is deposited on the resistive material layer. The resistive material layer is then subjected to a thermal treatment at a pre-selected temperature higher than 350 degrees Celsius in a hydrogen or deuterium atmosphere. The capping layer and the resistive material layer are patterned to form a thin film resistor on the first dielectric layer.

Abstract: a composite barrier film, comprising: an ultra-thin barrier film, wherein the ultra-thin barrier film is capable of being water-resistant and oxygen-resistant; and a protection film, being attached on the ultra-thin barrier film for increasing the stiffness of the ultra-thin barrier film, wherein a thickness of the ultra-thin barrier film is less than a thickness of the protection film.

Abstract: The present invention provides methods of hypo-acylated lipopolysaccharide (LPS) for improving anti-oxidation and preventing/treating endotoxemia and diseases associated with endotoxemia.

Abstract: Devices, systems, and techniques for analyzing video information to objectively identify patient behavior are disclosed. A system may analyze obtained video information of patient motion during a period of time to track one or more anatomical regions through a plurality of frames of the video information and calculate one or more movement parameters of the one or more anatomical regions. The system may also compare the one or more movement parameters to respective criteria for each of a plurality of predetermined patient behaviors and identify the patient behaviors that occurred during the period of time. In some examples, a device may control therapy delivery according to the identified patient behaviors and/or sensed parameters previously calibrated based on the identified patient behaviors.

Abstract: A light guide structure is configured in a lighting device of a mobile vehicle. The light guide structure comprises a light injecting surface and a light emitting surface. The light emitting surface comprises a middle section and two side sections deployed respectively at opposite ends of the middle section. The side sections have a plurality of jagged protrusions forming a light guiding area. The extending direction of the jagged protrusions intersects with the light emitting direction. A light source module forms an irradiation area by the light guide structure, the light guiding area extending the width of both sides of the irradiation area, the beam contour being enlarged evenly. The disclosure also provides a headlight structure, a light source module having the light guide structure and a convex lens configured sequentially in the light emitting direction.

Abstract: A method of manufacturing a die package structure includes steps described below. A conductive substrate with a plurality of trenches is provided. A die is disposed in each of the trenches. A conductive layer is formed covering the dies and the conductive substrate. A patterned photoresist layer with a plurality of openings is formed exposing a plurality of areas of the conductive layer. A mask is formed on each of the areas of the conductive layer. The patterned photoresist layer is removed after forming the masks. By using the masks, the conductive layer and the conductive substrate under thereof are selectively etched to a predetermined depth to form a plurality of conductive bumps and a plurality of electrodes, in which a remaining of the conductive substrate includes a bottom substrate, the electrodes and the conductive bumps. An upper sealing layer is formed covering the bottom substrate and the dies.

Abstract: In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode.

Abstract: A method of manufacturing a die package structure includes steps described below. A conductive substrate with a plurality of trenches is provided. A die is disposed in each of the trenches. A conductive layer is formed covering the dies and the conductive substrate. A patterned photoresist layer with a plurality of openings is formed exposing a plurality of areas of the conductive layer. A mask is formed on each of the areas of the conductive layer. The patterned photoresist layer is removed after forming the masks. By using the masks, the conductive layer and the conductive substrate under thereof are selectively etched to a predetermined depth to form a plurality of conductive bumps and a plurality of electrodes, in which a remaining of the conductive substrate includes a bottom substrate, the electrodes and the conductive bumps. An upper sealing layer is formed covering the bottom substrate and the dies.

Abstract: Various embodiments of the present application are directed towards a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory device, as well as a method for forming the MFMIS memory device. According to some embodiments of the MFMIS memory device, a first source/drain region and a second source/drain region are vertically stacked. An internal gate electrode and a semiconductor channel overlie the first source/drain region and underlie the second source/drain region. The semiconductor channel extends from the first source/drain region to the second source/drain region, and the internal gate electrode is electrically floating. A gate dielectric layer is between and borders the internal gate electrode and the semiconductor channel. A control gate electrode is on an opposite side of the internal gate electrode as the semiconductor channel and is uncovered by the second source/drain region. A ferroelectric layer is between and borders the control gate electrode and the internal gate electrode.

Abstract: A memory device includes a substrate, word line layers, insulating layers, and memory cells. The word line layers are stacked above the substrate. The insulating layers are stacked above the substrate respectively alternating with the word line layers. The memory cells are distributed along a stacking direction of the word line layers and the insulating layers perpendicularly to a major surface of the substrate. Each memory cell includes a source line electrode and a bit line electrode, a first oxide semiconductor layer, and a second oxide semiconductor layer. The first oxide semiconductor layer is peripherally surrounded by one of the word line layers, the source line electrode, and the bit line electrode. The second oxide semiconductor layer is disposed between the one of the word line layers and the first oxide semiconductor layer.

Abstract: A tridimensional memory cell array includes vertically stacked first conductive lines, vertically stacked second conductive lines, and first and second flights of steps. First and second conductive lines extend along a first direction. The second conductive lines are disposed at a distance along a second direction from the first conductive lines. First and second directions are orthogonal. Along the first direction, the first flights are disposed at opposite ends of the first conductive lines and the second flights are disposed at opposite ends of the second conductive lines. The first and second flights include landing pads and connective lines alternately disposed along the first direction. The landing pads are wider than the connective lines along the second direction. Along the second direction, landing pads of the first flights face connective lines of the second flights and landing pads of the second flights face connective lines of the first flights.